US5750426A
Expired / Lapsed
US
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Method of making MOS precision capacitor with low voltage coefficient
Assignee: IXYS Intl Ltd
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Filing: 1996-10-24
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Granted: 1998-05-12
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Expires: 2016-10-24
Abstract
Abstract A MOS precision capacitor is formed in an integrated circuit including a p-mos and n-mos transistor without adding to the process steps used in forming the p-mos and n-mos transistor. The MOS precision capacitor includes a n-well formed concurrently with a n-well of the p-mos transistor, a n-type region formed concurrently with a threshold adjust region of the p-mos transistor, an oxide layer formed concurrently with gate oxide layers of the p-mos and n-mos transistors, a first electrode formed over the n-type region, at least one n+ region formed concurrently with source and drain regions of the n-mos transistor by self aligning to the sidewall of the first electrode, and a second electrode connected to the at least one n+ region. Good gate oxide tracking between the MOS precision capacitor, the p-mos transistor, and the n-mos transistor, is provided by forming the n-type region of the MOS precision capacitor with a dopant concentration approximately equal to that of the threshold adjust region of the p-mos transistor, and approximately within an order of magnitude of that of the n-mos transistor. Good ground isolation for the MOS precision capacitor is provided by forming the MOS precision capacitor in its own n-well. Low voltage and signal frequency dependency for the MOS precision capacitor is provided by respectively forming the n-type and n+ regions between the first and second electrodes of the MOS precision capacitor such that their respective dopant concentrations are greater than that of the n-well.
Inventors
- 👤 Kamal Rajkanan
- 👤 Bruno Kranzen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:33
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047; H10D1/60; H10D1/62; H10D1/66; H10D84/00; H10D84/201; H10D84/204; H10D84/212; H10D84/80; H10D84/811; H10D84/813
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
271 words
A method of forming a precision capacitor in an integrated circuit including a p-mos transistor and a complementary n-mos transistor, wherein said precision capacitor, said p-mos transistor, and said n-mos transistor are respectively formed in first, second, and third regions of a semiconductor wafer including said integrated circuit, comprising: forming, in a same mask step, a n-well in said first region where said precision capacitor is to be formed, and a n-well in said second region where said p-mos transistor is to be formed, forming a gate oxide layer covering said first, second, and third regions of said semiconductor wafer, forming a first electrode of said precision capacitor over the gate oxide layer formed over said n-well formed in said first region of said semiconductor wafer, and forming a gate electrode of said n-mos transistor over the gate oxide layer formed over said third region of said semiconductor wafer, forming, in a same mask step, a first n-type region self aligned to said first electrode of said precision capacitor in said n-well formed in said first region of said semiconductor wafer such that said first n-type region has a dopant concentration greater than said n-well formed in said first region, and a second n-type region self aligned to said gate electrode of said n-mos transistor in said third region of said semiconductor wafer such that said second n-type region has a dopant concentration greater than said n-well formed in said third region, and forming a second electrode of said precision capacitor by connecting said second electrode to said first n-type region self aligned to said first electrode of said precision capacitor.
Claim 2
Independent Claim
271 words
A method of forming a precision capacitor in an integrated circuit including a p-mos transistor and a complementary n-mos transistor, wherein said precision capacitor, said p-mos transistor, and said n-mos transistor are respectively formed in first, second, and third regions of a semiconductor wafer including said integrated circuit, comprising: forming, in a same mask step, a n-well in said first region where said precision capacitor is to be formed, and a n-well in said second region where said p-mos transistor is to be formed, forming a gate oxide layer covering said first, second, and third regions of said semiconductor wafer, forming a first electrode of said precision capacitor over the gate oxide layer formed over said n-well formed in said first region of said semiconductor wafer, and forming a gate electrode of said n-mos transistor over the gate oxide layer formed over said third region of said semiconductor wafer, forming, in a same mask step, a first n-type region self aligned to said first electrode of said precision capacitor in said n-well formed in said first region of said semiconductor wafer such that said first n-type region has a dopant concentration greater than said n-well formed in said first region, and a second n-type region self aligned to said gate electrode of said n-mos transistor in said third region of said semiconductor wafer such that said second n-type region has a dopant concentration greater than said n-well formed in said third region, and forming a second electrode of said precision capacitor by connecting said second electrode to said first n-type region self aligned to said first electrode of said precision capacitor.
Claim 3
Dependent Claim
135 words
The method as recited in claim 1, further comprising forming, in a same mask step performed after said precision capacitor and p-mos transistor n-well forming step and before said gate oxide layer forming step, a third n-type region in said n-well formed in said first region of said semiconductor wafer such that said third n-type region has a dopant concentration less than said first n-type region and greater than said n-well formed in said first region, and a n-type threshold adjust region in said n-well formed in said second region of said semiconductor wafer, wherein said first precision capacitor electrode forming step comprises forming a first electrode of said precision capacitor over the gate oxide layer formed over said third n-type region formed in said n-well formed in said first region of said semiconductor wafer.
Claim 4
Dependent Claim
98 words
The method as recited in claim 2, further comprising blanket implanting, before said precision capacitor and p-mos transistor n-well forming step, a dopant into said first, second, and third regions of said semiconductor wafer such that the dopant implanted into said third region acts as a threshold adjust region for said n-mos transistor formed in said third region, and the dopant implanted into said first region has a dopant concentration approximately within an order of magnitude of the dopant concentration in said third n-type region formed in said n-well formed in said first region of said semiconductor wafer.
Claim 5
Dependent Claim
98 words
The method as recited in claim 2, further comprising blanket diffusing, before said precision capacitor and p-mos transistor n-well forming step, a dopant into said first, second, and third regions of said semiconductor wafer such that the dopant implanted into said third region acts as a threshold adjust region for said n-mos transistor formed in said third region, and the dopant implanted into said first region has a dopant concentration approximately within an order of magnitude of the dopant concentration in said third n-type region formed in said n-well formed in said first region of said semiconductor wafer.
Claim 6
Dependent Claim
283 words
The method as recited in claim 1, wherein said first and second n-type regions forming step comprise: forming, in a same mask step, a first lightly doped n-type region self aligned to said first electrode of said precision capacitor in said n-well formed in said first region of said semiconductor wafer such that said first lightly doped n-type region has a dopant concentration less than said n-well formed in said first region, and a second lightly doped n-type region self aligned to said gate electrode of said n-mos transistor in said third region of said semiconductor wafer such that said second lightly doped n-type region has a dopant concentration less than said n-well formed in said third region, forming a spacer on said first electrode of said precision capacitor, and a spacer on said gate electrode of said n-mos transistor, and forming, in a same mask step, a first heavily doped n-type region self aligned to said spacer formed on said first electrode of said precision capacitor such that said first heavily doped n-type region has a dopant concentration greater than said n-well formed in said first region, and a second heavily doped n-type region self aligned to said spacer formed on said gate electrode of said n-mos transistor such that said second heavily doped n-type region has a dopant concentration greater than said n-well formed in said third region, wherein said first lightly doped and first heavily doped n-type regions form said first n-type region in said n-well formed in said first region of said semiconductor wafer, and said second lightly doped and second heavily doped n-type regions form said second n-type region formed in said third region of said semiconductor wafer.
Claim 7
Dependent Claim
76 words
The method as recited in claim 1, wherein said precision capacitor first electrode and said n-mos transistor gate electrode forming steps comprise forming, in a same mask step, a first electrode of said precision capacitor over the gate oxide layer formed over said n-well formed in said first region of said semiconductor wafer, and forming a gate electrode of said n-mos transistor over the gate oxide layer formed over said third region of said semiconductor wafer.
Claim 8
Dependent Claim
54 words
The method as recited in claim 1, wherein said precision capacitor n-well and p-mos transistor n-well forming step comprises forming, during a same ion implantation, a n-well in said first region where said precision capacitor is to be formed, and a n-well in said second region where said p-mos transistor is to be formed.
Claim 9
Dependent Claim
110 words
The method as recited in claim 1, wherein said first and second n-type regions forming step comprises forming, during a same ion implantation, a first n-type region self aligned to said first electrode of said precision capacitor in said n-well formed in said first region of said semiconductor wafer such that said first n-type region has a dopant concentration greater than said n-well formed in said first region, and a second n-type region self aligned to said gate electrode of said n-mos transistor in said third region of said semiconductor wafer such that said second n-type region has a dopant concentration greater than said n-well formed in said third region.
Claim 10
Dependent Claim
127 words
The method as recited in claim 2, wherein said third n-type region and n-type threshold adjust region forming step comprises forming, during a same ion implantation, a third n-type region in said n-well formed in said first region of said semiconductor wafer such that said third n-type region has a dopant concentration less than said first n-type region and greater than said n-well formed in said first region, and a n-type threshold adjust region in said n-well formed in said second region of said semiconductor wafer, wherein said first precision capacitor electrode forming step comprises forming a first electrode of said precision capacitor over the gate oxide layer formed over said third n-type region formed in said n-well formed in said first region of said semiconductor wafer.
Claim 11
Dependent Claim
120 words
The method as recited in claim 5, wherein said first and second lightly doped n-type regions forming step comprises forming, during a same ion implantation, a first lightly doped n-type region self aligned to said first electrode of said precision capacitor in said n-well formed in said first region of said semiconductor wafer such that said first lightly doped n-type region has a dopant concentration less than said n-well formed in said first region, and a second lightly doped n-type region self aligned to said gate electrode of said n-mos transistor in said third region of said semiconductor wafer such that said second lightly doped n-type region has a dopant concentration less than said n-well formed in said third region.
Claim 12
Dependent Claim
161 words
The method as recited in claim 5, wherein said first and second heavily doped n-type regions forming step comprises forming, during a same ion implantation, a first heavily doped n-type region self aligned to said spacer formed on said first electrode of said precision capacitor such that said first heavily doped n-type region has a dopant concentration greater than said n-well formed in said first region, and a second heavily doped n-type region self aligned to said spacer formed on said gate electrode of said n-mos transistor such that said second heavily doped n-type region has a dopant concentration greater than said n-well formed in said third region, wherein said first lightly doped and first heavily doped n-type regions form said first n-type region in said n-well formed in said first region of said semiconductor wafer, and said second lightly doped and second heavily doped n-type regions form said second n-type region formed in said third region of said semiconductor wafer.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |