US5748645A
Expired / Lapsed
US
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Clock scan design from sizzle global clock and method therefor
Assignee: NXP USA Inc
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Filing: 1996-05-29
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Granted: 1998-05-05
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Expires: 2016-05-29
Abstract
Abstract A scan based test methodology generates conventional functional clocks (CLK1 and CLK2) and test clocks (CLKA and CLKB) from a single input clock (GCLK). The methodology allows an integrated circuit (10) designed according to it to be tested at the part's operating frequency. Also, the test methodology is compatible with known test methodologies such as level sensitive scan design ("LSSD"). The pre-existing body of test programs and equipment can be used with a circuit incorporating the invention. The single clock requirement also simplifies design.
Inventors
- 👤 Craig C. Hunter
- 👤 Russell A. Reininger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:06
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318552
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
166 words
A single clock scan design circuit for testing a synchronous circuit, the synchronous circuit comprising a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a first test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock, the single clock scan design circuit comprising: first circuitry receiving a single clock and generating the first test clock therefrom responsive to at least one control signal; second circuitry receiving the single clock and generating the first functional clock therefrom responsive to the at least one control signal; and third circuitry receiving the single clock signal and generating the second functional clock from the at least one control signal.
Claim 2
Dependent Claim
166 words
A single clock scan design circuit for testing a synchronous circuit, the synchronous circuit comprising a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a first test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock, the single clock scan design circuit comprising: first circuitry receiving a single clock and generating the first test clock therefrom responsive to at least one control signal; second circuitry receiving the single clock and generating the first functional clock therefrom responsive to the at least one control signal; and third circuitry receiving the single clock signal and generating the second functional clock from the at least one control signal.
Claim 3
Dependent Claim
40 words
The single clock scan design circuit claim 1 wherein one of the plurality of latches is a *L2 further comprising: fourth circuitry receiving the single clock and generating a second clock therefrom responsive to the at least one control signal.
Claim 4
Dependent Claim
131 words
An integrated circuit comprising: a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a first test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock; and at least one first clock regenerator, the at least one first clock regenerator receiving a single clock and at least one control signal, the at least one first clock regenerator generating the first functional clock, the first test clock, and the second functional clock.
Claim 5
Dependent Claim
131 words
An integrated circuit comprising: a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a first test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock; and at least one first clock regenerator, the at least one first clock regenerator receiving a single clock and at least one control signal, the at least one first clock regenerator generating the first functional clock, the first test clock, and the second functional clock.
Claim 6
Dependent Claim
65 words
The integrated circuit of claim 3 further comprising: at least one *L2 latch, the at least one *L2 latch capturing functional data responsive to a second test clock; and at least one second clock regenerator, the at least one second clock regenerator receiving the single clock and the at least one control signal, the at least one first clock regenerator generating the second test clock.
Claim 7
Independent Claim
214 words
A method of testing an integrated circuit, the integrated circuit comprising a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock, the method comprising the steps of: during a first time, shifting a test vector into the plurality of latches by periodically asserting the test clock, the test clock generated from a single clock and at least one control signal; during a second time, applying the test vector stored in the plurality of latches to logic, the outputs of the plurality of latches coupled to the plurality of latches; during a third time, capturing an output ("captured output") from the logic by the plurality of latches by asserting the first functional clock, the first functional clock generated from the single clock and the at least one control signal; and during a fourth time, shifting out the captured output from the plurality of latches.
Claim 8
Independent Claim
214 words
A method of testing an integrated circuit, the integrated circuit comprising a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock, the method comprising the steps of: during a first time, shifting a test vector into the plurality of latches by periodically asserting the test clock, the test clock generated from a single clock and at least one control signal; during a second time, applying the test vector stored in the plurality of latches to logic, the outputs of the plurality of latches coupled to the plurality of latches; during a third time, capturing an output ("captured output") from the logic by the plurality of latches by asserting the first functional clock, the first functional clock generated from the single clock and the at least one control signal; and during a fourth time, shifting out the captured output from the plurality of latches.
Claim 9
Dependent Claim
27 words
The method of claim 5 wherein the step of shifting a test vector comprises the step of: periodically asserting the test clock and the second functional clock.
Claim 10
Dependent Claim
27 words
The method of claim 6 wherein the step of capturing an output comprises the step of: periodically asserting the first functional clock and the second functional clock.
Claim 11
Dependent Claim
27 words
The method of claim 5 wherein the step of capturing an output comprises the step of: periodically asserting the first functional clock and the second functional clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |