US5394403A
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Fully testable chip having self-timed memory arrays
Assignee: Sun Microsystems Inc
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Filing: 1992-06-12
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Granted: 1995-02-28
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Expires: 2012-06-12
Abstract
Abstract A method and apparatus is provided for testing self timed memory arrays which does not affect the state of cells within the arrays not being tested. Each memory array has a plurality of control, address and data registers which are coupled to the respective control, address and data lines into the memory array. A timing generator circuit receives an external clock pulse and provides the self-timed clock pulses to the memory array. During the shift mode, the control, address and data registers are chained together such that data for testing can be scanned serially into the registers. In order to prevent unplanned array modification operations from occurring during the shift mode because a bit shifted into the write-enable or clear register at the time a clock pulse derived from the timing circuitry is generated, a logic means is provided to disable all clock pulses during the shift mode. A separate shift clock pulse is provided during shift mode to shift the test information into the control, address and data registers. Once the information is shifted in, a separate test clock pulse is issued to cause the operation indicated by the data in the address, control and data registers to be performed. Thus, the operation identified by the control address and data registers is performed without affecting the state of the control registers of adjacent memory arrays and without affecting the state of other memory cells and components on the chip while maintaining the same temporal state of the chip.
Inventors
- 👤 Michael F. Klein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:16
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/32; G11C29/12015; G11C29/52
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
243 words
A self-timed memory array comprising at least one memory cell, said memory array comprising control registers and control lines coupled to the control registers to control operations on the array of the memory cell, address registers and address lines coupled to the address registers to identify the address of the memory cell at which an operation is to be performed, data lines for supplying data to and reading data from the memory cell, and timing generator circuitry for receiving an external clock pulse from an external clock and providing self-timed clock inputs for performing operations on cells in the array, said memory array further comprising an apparatus for providing for testing of the array, said apparatus comprising: shift means for chaining the control registers and address registers such that information can be serially shifted into and out of the control and address registers, said shift means being enabled during a shift mode; means for disabling memory array operations while information is serially shifted into and out of the control and address registers; a test clocking means for providing a test clock pulse to the memory array to be tested to cause an operation dictated by the information shifted into the control registers to be performed at the address identified in the address registers; wherein a test operation is performed on a memory cell without affecting other memory cells of the array and maintaining a common temporal state with the address and control registers.
Claim 2
Dependent Claim
243 words
A self-timed memory array comprising at least one memory cell, said memory array comprising control registers and control lines coupled to the control registers to control operations on the array of the memory cell, address registers and address lines coupled to the address registers to identify the address of the memory cell at which an operation is to be performed, data lines for supplying data to and reading data from the memory cell, and timing generator circuitry for receiving an external clock pulse from an external clock and providing self-timed clock inputs for performing operations on cells in the array, said memory array further comprising an apparatus for providing for testing of the array, said apparatus comprising: shift means for chaining the control registers and address registers such that information can be serially shifted into and out of the control and address registers, said shift means being enabled during a shift mode; means for disabling memory array operations while information is serially shifted into and out of the control and address registers; a test clocking means for providing a test clock pulse to the memory array to be tested to cause an operation dictated by the information shifted into the control registers to be performed at the address identified in the address registers; wherein a test operation is performed on a memory cell without affecting other memory cells of the array and maintaining a common temporal state with the address and control registers.
Claim 3
Dependent Claim
75 words
The memory array as set forth in claim 1, wherein said shift means for chaining further comprises means for coupling a last register of a first memory array to a first register of a second memory array such that data can be serially shifted in to the second memory array by shifting data through the control and address registers of the first memory array to the control and address registers of the second memory array.
Claim 4
Dependent Claim
26 words
The memory array as set forth in claim 1, further comprising a scan signal line which indicates when the memory array is in the shift mode.
Claim 5
Dependent Claim
30 words
The memory array as set forth in claim 1, wherein said means for disabling memory array operations disables the external clock to the timing generator circuitry during the shift mode.
Claim 6
Dependent Claim
31 words
The memory array as set forth in claim 1, wherein said test clocking means provides the test clock pulse after information has been serially shifted into the address and control registers.
Claim 7
Dependent Claim
33 words
The memory array as set forth in claim 1, further comprising a shift clock for providing shift clock pulses for the shift means to serially shift information into the address and control registers.
Claim 8
Dependent Claim
37 words
The memory array as set forth in claim 1, wherein said means for disabling memory operations enables the external clock to the timing generator's circuitry after the shift mode is finished and the test clock is asserted.
Claim 9
Dependent Claim
29 words
The memory array as set forth in claim 1, further comprising data registers coupled to the data lines for supplying data to and receiving data from the memory array.
Claim 10
Dependent Claim
43 words
The memory array as set forth in claim 8 wherein the memory array is coupled to a JTAG test access port (TAP) for receiving information external to the array to be serially shifted into and out of the address, control and data registers.
Claim 11
Dependent Claim
238 words
In a self-timed memory array comprising at least one memory cell, the memory array comprising control registers and control lines coupled to the control registers to control operations on the array of memory cells, address registers and address lines coupled to the address registers to identify the address of a memory cell at which an operation is to be performed, data lines for supplying data to and reading data from a memory cell, and timing generator circuitry for receiving an external clock pulse and for providing self-timed clock inputs for performing operations on memory cells in the memory array, a process for testing the memory array, comprising the steps of: chaining the control registers and address registers such that information can be serially shifted into and out of the control and address registers during a shift mode; shifting serially information into the control registers and address registers; disabling memory array operations while data is serially shifted into and out of the control and address registers; issuing a test clock pulse to the memory array to be tested once data is serially shifted into the registers to cause an operation dictated by the information shifted into the control registers be performed at the address identified in the address registers; wherein a test operation is performed on a memory cell without affecting other memory cells of the array and maintaining a common temporal state with the address and control registers.
Claim 12
Dependent Claim
238 words
In a self-timed memory array comprising at least one memory cell, the memory array comprising control registers and control lines coupled to the control registers to control operations on the array of memory cells, address registers and address lines coupled to the address registers to identify the address of a memory cell at which an operation is to be performed, data lines for supplying data to and reading data from a memory cell, and timing generator circuitry for receiving an external clock pulse and for providing self-timed clock inputs for performing operations on memory cells in the memory array, a process for testing the memory array, comprising the steps of: chaining the control registers and address registers such that information can be serially shifted into and out of the control and address registers during a shift mode; shifting serially information into the control registers and address registers; disabling memory array operations while data is serially shifted into and out of the control and address registers; issuing a test clock pulse to the memory array to be tested once data is serially shifted into the registers to cause an operation dictated by the information shifted into the control registers be performed at the address identified in the address registers; wherein a test operation is performed on a memory cell without affecting other memory cells of the array and maintaining a common temporal state with the address and control registers.
Claim 13
Dependent Claim
67 words
The process for testing the memory array as set forth in claim 10, further comprising the step of coupling a last register of a first memory array to a first register of a second memory array such that information can be serially scanned into the second memory array by shifting information through the registers of the first memory array to the registers of the second memory array.
Claim 14
Dependent Claim
47 words
The process for testing the memory array as set forth in claim 10, further comprising the step of issuing a shift mode signal, wherein said step of serially shifting information serially shifts information into the control registers and address registers while said shift mode signal is issued.
Claim 15
Dependent Claim
37 words
The process for testing the memory array as set forth in claim 10, wherein the step of disabling memory array operations comprises the step of disabling during the shift mode an external clock coupled to the array.
Claim 16
Dependent Claim
32 words
The process for testing the memory array as set forth in claim 10, further comprising the step of providing shift clock pulses to serially shift data into the address and control registers.
Claim 17
Dependent Claim
28 words
The process for testing the memory array as set forth in claim 10, further comprising the step of enabling the external clock after the shift mode is finished.
Claim 18
Dependent Claim
81 words
The process for testing the memory array as set forth in claim 10, wherein data registers are coupled to data lines for supplying data to and receiving data from the memory array, said step of chaining further comprises the steps of chaining the data registers to the control registers and address register such that information is serially shifted into and out of the registers, and said step of shifting serially shifts information into the control registers, address registers and data registers.
Claim 19
Dependent Claim
31 words
The process for testing the memory array as set forth in claim 16, further comprising the step of shifting information from the data registers after the test clock pulse is issued.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |