LCD driving apparatus allowing for multiple aspect resolution

Claim 2

A driving circuit for sequentially scanning a plurality of scanning signal lines, the driving circuit comprising a shift register having a plurality of unit registers and nodes, each of the plurality of unit registers being connected to the corresponding scanning signal line, a start signal input to a selected node at a beginning of a set of consecutive nodes being sequentially shifted to an adjacent unit register in the set of consecutive registers based on a standard signal, the adjacent unit register connected to the selected node being allowed to be in a non-operational state based on a first state of a control signal applied to the selected node, and wherein, when the control signal has the first state, a subsequent node in the set of consecutive registers receives a different control signal for rendering operational at least some of the unit registers which follow the subsequent node in the set of consecutive registers, the start signal input to the selected node being output from the selected node and eventually to the subsequent node based on a second state of the control signal.

Claim 3

A driving circuit for driving and controlling a plurality of scanning signal lines and a plurality of sampling gates for sampling a data signal, the driving circuit comprising: a shift register having a plurality of unit registers, the plurality of unit registers being connected to one of the corresponding scanning signal lines and the corresponding sampling gates; wherein the shift register includes a start signal input to a selected node at a beginning of a set of consecutive nodes being sequentially shifted to an adjacent unit register in the set of consecutive registers based on a standard signal, the adjacent unit register connected to the selected node being allowed to be in a non-operational state based on a first state of a control signal applied to the selected node, and wherein, when the control signal has the first state, a subsequent node in the set of consecutive registers receives a different control signal for rendering operational at least some of the unit registers which follow the subsequent node in the set of consecutive registers, the start signal input to the selected node being output from the selected node and eventually to the subsequent node based on a second state of the control signal, and a logic gate array for receiving a holding signal which each unit register of the shift register holds, and outputting the holding signal to a buffer as one of a scanning signal and a sampling gate control signal, and wherein a start signal is stored in the unit register to which the start signal is input via the selected node, and the start signal is shifted from the unit register in which the start signal is stored to a unit register adjacent to the unit register in which the start signal is stored based on the standard signal and wherein the logic gate array outputs the signal output from the unit register to a buffer in a logic gate receiving a signal output from the unit register to which the start signal is shifted, and outputs a signal to the buffer in a logic gate receiving a signal output from the unit register to which the start signal is not shifted.

Claim 4

A driving circuit for driving and controlling a plurality of scanning signal lines and a plurality of sampling gates for sampling a data signal, the driving circuit comprising: a shift register having a plurality of unit registers, the plurality of unit registers being connected to one of the corresponding scanning signal lines and the corresponding sampling gates; wherein the shift register includes a start signal input to a selected node at a beginning of a set of consecutive nodes being sequentially shifted to an adjacent unit register in the set of consecutive registers based on a standard signal, the adjacent unit register connected to the selected node being allowed to be in a non-operational state based on a first state of a control signal applied to the selected node, and wherein, when the control signal has the first state, a subsequent node in the set of consecutive registers receives a different control signal for rendering operational at least some of the unit registers which follow the subsequent node in the set of consecutive registers, the start signal input to the selected node being output from the selected node and eventually to the subsequent node based on a second state of the control signal, and a logic gate array for receiving a holding signal which each unit register of the shift register holds, and outputting the holding signal to a buffer as one of a scanning signal and a sampling gate control signal, and wherein a start signal is stored in the unit register to which the start signal is input via the selected node, and the start signal is shifted from the unit register in which the start signal is stored to a unit register adjacent to the unit register in which the start signal is stored based on the standard signal and wherein the logic gate array outputs the signal output from the unit register to a buffer in a logic gate receiving a signal output from the unit register to which the start signal is shifted, and outputs a signal to the buffer in a logic gate receiving a signal output from the unit register to which the start signal is not shifted.

Claim 5

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving circuit and the data driving circuit includes a shift register having a plurality of unit registers and nodes, each of the plurality of unit registers being connected to the corresponding scanning signal line, a start signal input to a selected node at a beginning of a set of consecutive nodes being sequentially shifted to an adjacent unit register in the set of consecutive registers based on a standard signal, the adjacent unit register connected to the selected node being allowed to be in a non-operational state based on a first state of a control signal applied to the selected node, and wherein, when the control signal has the first state, a subsequent node in the set of consecutive registers receives a different control signal for rendering operational at least some of the unit registers which follow the subsequent node in the set of consecutive registers, the start signal input to the selected node being output from the selected node, and eventually to the subsequent node based on a second state of the control signal, wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching.

Claim 6

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving circuit and the data driving circuit includes a shift register having a plurality of unit registers and nodes, each of the plurality of unit registers being connected to the corresponding scanning signal line, a start signal input to a selected node at a beginning of a set of consecutive nodes being sequentially shifted to an adjacent unit register in the set of consecutive registers based on a standard signal, the adjacent unit register connected to the selected node being allowed to be in a non-operational state based on a first state of a control signal applied to the selected node, and wherein, when the control signal has the first state, a subsequent node in the set of consecutive registers receives a different control signal for rendering operational at least some of the unit registers which follow the subsequent node in the set of consecutive registers, the start signal input to the selected node being output from the selected node, and eventually to the subsequent node based on a second state of the control signal, wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching.

Claim 7

A display device according to claim 3, wherein at least one of the scanning signal driving circuit and the data driving circuit is obtained by serially connecting a plurality of unit registers corresponding to one of the scanning signal lines and the data signal lines, and has a shift register for shifting a start signal input to a predetermined node to an adjacent unit register based on a standard signal; the shift register has an terminal node and a middle node; and the start signal input to the terminal node and the middle node are controlled by a control signal.

Claim 8

A display device according to claim 3, wherein a data circuit sequential drives a plurality of sampling gates for sampling a data signal; at least one of the scanning signal driving circuit and the data driving circuit includes: a shift register having a plurality of unit registers, the plurality of unit registers being connected to one of the corresponding scanning signal lines and the corresponding sampling gates, one of the plurality of unit registers receiving a start signal via a predetermined middle node, the shift register for shifting a start signal stored in a unit register to a unit register adjacent to the unit register in which the start signal is stored; a logic gate array for receiving a holding signal which each unit register of the shift register holds, and outputting one of a scanning signal and a sampling gate control signal to a buffer; in the case where a first logic gate in the logic gate array receives a first signal output from the unit register which shifts the start signal, the first logic gate outputs the first signal to a buffer in the logic gate array; and in the case where a second logic gate in the logic gate array receives a second signal output from the unit register which does not shift the start signal, the second logic gate outputs the second signal to a buffer in the logic gate array.

Claim 9

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein a data circuit sequentially drives a plurality of sampling gates for sampling a data signal; wherein at least one of the scanning signal driving circuits and the data driving circuit includes: a shift register having a plurality of unit registers, the plurality of unit registers being connected to one of the corresponding scanning signal lines and the corresponding sampling gates, one of the plurality of unit registers receiving a start signal via a predetermined middle node, the shift register for shifting a start signal stored in a unit register to a unit register adjacent to the unit register in which the start signal is stored; a logic gate array for receiving a holding signal which each unit register of the shift register holds, and outputting one of a scanning signal and a sampling gate control signal to a buffer; in the case where a first logic gate in the logic gate array receives a first signal output from the unit register which shifts the stat signal, the first logic gate outputs the first signal to a buffer in the logic gate array; and in the case where a second logic gate in the logic gate array receives a second signal output from the unit register which does not shift the start signal, the second logic gate outputs the second signal to a buffer in the logic gate array; wherein the shift register has a terminal node and selects either the terminal node or the middle node based on a control signal, and the selected node receives the start signal.

Claim 10

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein a data circuit sequentially drives a plurality of sampling gates for sampling a data signal; wherein at least one of the scanning signal driving circuits and the data driving circuit includes: a shift register having a plurality of unit registers, the plurality of unit registers being connected to one of the corresponding scanning signal lines and the corresponding sampling gates, one of the plurality of unit registers receiving a start signal via a predetermined middle node, the shift register for shifting a start signal stored in a unit register to a unit register adjacent to the unit register in which the start signal is stored; a logic gate array for receiving a holding signal which each unit register of the shift register holds, and outputting one of a scanning signal and a sampling gate control signal to a buffer; in the case where a first logic gate in the logic gate array receives a first signal output from the unit register which shifts the stat signal, the first logic gate outputs the first signal to a buffer in the logic gate array; and in the case where a second logic gate in the logic gate array receives a second signal output from the unit register which does not shift the start signal, the second logic gate outputs the second signal to a buffer in the logic gate array; wherein the shift register has a terminal node and selects either the terminal node or the middle node based on a control signal, and the selected node receives the start signal.

Claim 11

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein at least one of the scanning signal driving circuit and the data driving circuit is obtained by serially connecting a plurality of unit registers corresponding to one of the scanning signal lines and the data signal lines, and has a shift register for shifting a start signal input to a predetermined node to an adjacent unit register based on a standard signal; the shift register has a terminal node and a middle node; and the start signal input to the terminal node and the middle node are controlled by a control signal; wherein the shift register can perform a shift operation in both directions.

Claim 12

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein at least one of the scanning signal driving circuit and the data driving circuit is obtained by serially connecting a plurality of unit registers corresponding to one of the scanning signal lines and the data signal lines, and has a shift register for shifting a start signal input to a predetermined node to an adjacent unit register based on a standard signal; the shift register has a terminal node and a middle node; and the start signal input to the terminal node and the middle node are controlled by a control signal; wherein the shift register can perform a shift operation in both directions.

Claim 13

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein at least one of the scanning signal driving circuit and the data driving circuit is obtained by serially connecting a plurality of unit registers corresponding to one of the scanning signal lines and the data signal lines, and has a shift register for shifting a start signal input to a predetermined node to an adjacent unit register based on a standard signal; the shift register has a terminal node and a middle node; and the start signal input to the terminal node and the middle node are controlled by a control signal; first delay time adjusting means for adjusting a first amount of delay of a signal output from the node which receives the start signal and a second amount of delay of the output signal from the unit register so as to equalize the first amount with the second amount.

Claim 14

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein at least one of the scanning signal driving circuit and the data driving circuit is obtained by serially connecting a plurality of unit registers corresponding to one of the scanning signal lines and the data signal lines, and has a shift register for shifting a start signal input to a predetermined node to an adjacent unit register based on a standard signal; the shift register has a terminal node and a middle node; and the start signal input to the terminal node and the middle node are controlled by a control signal; first delay time adjusting means for adjusting a first amount of delay of a signal output from the node which receives the start signal and a second amount of delay of the output signal from the unit register so as to equalize the first amount with the second amount.

Claim 15

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein a data circuit sequentially drives a plurality of sampling gates for sampling a data signal; wherein at least one of the scanning signal driving circuit and the data driving circuit includes: a shift register having a plurality of unit registers, the plurality of unit registers being connected to one of the corresponding scanning signal lines and the corresponding sampling gates, one of the plurality of unit registers receiving a start signal via a predetermined middle node, the shift register for shifting a start signal stored in a unit register to a unit register adjacent to the unit register in which the start signal is stored; a logic gate array for receiving a holding signal which each unit register of the shift register holds, and outputting one of a scanning signal and a sampling gate control signal to a buffer; in the case where a first logic gate in the logic gate array receives a first signal output from the unit register which shifts the start signal, the first logic gate outputs the first signal to a buffer in the logic gate array; and in the case where a second logic gate in the logic gate array receives a second signal output from the unit register which does not shift the start signal, the second logic gate outputs the second signal to a buffer in the logic gate array; a second delay time adjusting means for adjusting a first amount of delay of output signals from unit register which do not shift the start signal and a second amount of delay of output signals from unit register which shifts the start signal so as to equalize the first amount with the second amount.

Claim 16

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein a data circuit sequentially drives a plurality of sampling gates for sampling a data signal; wherein at least one of the scanning signal driving circuit and the data driving circuit includes: a shift register having a plurality of unit registers, the plurality of unit registers being connected to one of the corresponding scanning signal lines and the corresponding sampling gates, one of the plurality of unit registers receiving a start signal via a predetermined middle node, the shift register for shifting a start signal stored in a unit register to a unit register adjacent to the unit register in which the start signal is stored; a logic gate array for receiving a holding signal which each unit register of the shift register holds, and outputting one of a scanning signal and a sampling gate control signal to a buffer; in the case where a first logic gate in the logic gate array receives a first signal output from the unit register which shifts the start signal, the first logic gate outputs the first signal to a buffer in the logic gate array; and in the case where a second logic gate in the logic gate array receives a second signal output from the unit register which does not shift the start signal, the second logic gate outputs the second signal to a buffer in the logic gate array; a second delay time adjusting means for adjusting a first amount of delay of output signals from unit register which do not shift the start signal and a second amount of delay of output signals from unit register which shifts the start signal so as to equalize the first amount with the second amount.

Claim 17

A display device according to claim 3, wherein the display device sequentially drives and controls a plurality of gates for sampling a data signals; one of the scanning signal driving circuit and the data driving circuit includes: a decoder having a plurality of output nodes and outputting one of a first signal and a second signal to a predetermined output node based on a plurality of input signals; and a logic gate array for receiving a signal from each output node of the decoder and outputting the signal to a buffer as one of a scanning signal and a sampling gate control signal; and wherein the plurality of output nodes is classified into a first group and a second group wherein the first signal is output from the decoder to the logic gate array via the output node of the first group, wherein one of the first signal and the second signal is output from the decoder to the logic gate array via the output node of the second group, based on a control signal.

Claim 18

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein the display device sequentially drives and controls a plurality of gates for sampling a data signal; one of the scanning signal driving circuit and the data driving circuit includes: a decoder having a plurality of output nodes and outputting one of a first signal and a second signal to a predetermined output node based on a plurality of input signals; and a logic gate array for receiving a signal from each output node of the decoder and outputting the signal to a buffer as one of a scanning signal and a sampling gate control signal; and wherein the plurality of output nodes is classified into a first group and a second group wherein the first signal is output from the decoder to the logic gate array via the output node of the first group, wherein one of the first signal and the second signal is output from the decoder to the logic gate array via the output node of the second group, based on a control signal; first delay time adjusting means for adjusting a first amount of delay of a signal output from the output node of the first group and a second amount of delay of the output signal from the output node of the second group so as to equalize the first amount with the second amount.

Claim 19

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein the display device sequentially drives and controls a plurality of gates for sampling a data signal; one of the scanning signal driving circuit and the data driving circuit includes: a decoder having a plurality of output nodes and outputting one of a first signal and a second signal to a predetermined output node based on a plurality of input signals; and a logic gate array for receiving a signal from each output node of the decoder and outputting the signal to a buffer as one of a scanning signal and a sampling gate control signal; and wherein the plurality of output nodes is classified into a first group and a second group wherein the first signal is output from the decoder to the logic gate array via the output node of the first group, wherein one of the first signal and the second signal is output from the decoder to the logic gate array via the output node of the second group, based on a control signal; first delay time adjusting means for adjusting a first amount of delay of a signal output from the output node of the first group and a second amount of delay of the output signal from the output node of the second group so as to equalize the first amount with the second amount.

Claim 20

A display device according to claim 3, wherein a video signal corresponding to a blank area displayed in a marginal portion of the display screen is supplied from the data driving circuit to each data signal line during one of a horizontal blanking period and a vertical blanking period.

Claim 21

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein at least a part of the video signal corresponding to a blank area displayed in a marginal portion of the display screen is supplied to each data signal line during one of a horizontal blanking period and a vertical blanking period through another analog switch other than an analog switch which supplies a video signal from the data driving circuit to the data signal line.

Claim 22

A display device comprising: a display portion having a plurality of scanning signal lines and a plurality of data signal lines arranged so as to cross the plurality of scanning signal lines, and displaying an image by applying a voltage to an intersecting portion between the scanning signal line and the data signal line; a scanning signal driving circuit for sequentially scanning the plurality of scanning signal lines; a data driving circuit for sequentially driving the plurality of data signal lines; wherein at least one of the scanning signal driving and the data driving is controlled by a display switching signal, and a marginal area of a display screen is made to be blank regions by the display switching; wherein at least a part of the video signal corresponding to a blank area displayed in a marginal portion of the display screen is supplied to each data signal line during one of a horizontal blanking period and a vertical blanking period through another analog switch other than an analog switch which supplies a video signal from the data driving circuit to the data signal line.

Claim 23

A display device comprising: a plurality of scanning signal lines being classified into a predetermined first group and a predetermined second group; a plurality of data signal lines being classified into a predetermined first group and a predetermined second group; a gate driver for receiving a first control signal, for further receiving a first sampling control signal, for supplying a corresponding first scanning pulse signal to the plurality of scanning signal lines when the first control signal is in a first state, for supplying a corresponding second scanning pulse signal to the scanning signal lines of the predetermined first group and supplying a non-selection signal to the scanning signal lines of the predetermined second group based on the first sampling control signal when the first control signal is in a second state; and a source driver for receiving a second control signal, further receiving a second sampling control signal, supplying a corresponding first data pulse signal to the plurality of data signal lines when the second control signal is in a first state, supplying a corresponding second data pulse signal to the data signal lines of the predetermined first group, and supplying a marginal signal to the data signal lines of the predetermined second group based on the data control signal when the second control signal is in a second state; and wherein a width of the first scanning pulse signal is shorter than a width of the second scanning pulse signal; and wherein a width of the first data pulse signal is shorter than a width of the second data pulse signal.

Claim 24

A display device comprising: a plurality of scanning signal lines being classified into a predetermined first group and a predetermined second group; a plurality of data signal lines being classified into a predetermined first group and a predetermined second group; a gate driver for receiving a first control signal, for further receiving a first sampling control signal, for supplying a corresponding first scanning pulse signal to the plurality of scanning signal lines when the first control signal is in a first state, for supplying a corresponding second scanning pulse signal to the scanning signal lines of the predetermined first group and supplying a non-selection signal to the scanning signal lines of the predetermined second group based on the first sampling control signal when the first control signal is in a second state; and a source driver for receiving a second control signal, further receiving a second sampling control signal, supplying a corresponding first data pulse signal to the plurality of data signal lines when the second control signal is in a first state, supplying a corresponding second data pulse signal to the data signal lines of the predetermined first group, and supplying a marginal signal to the data signal lines of the predetermined second group based on the data control signal when the second control signal is in a second state; and wherein a width of the first scanning pulse signal is shorter than a width of the second scanning pulse signal; and wherein a width of the first data pulse signal is shorter than a width of the second data pulse signal.

Claim 25

A display device according to claim 14, wherein the non-selection signal is at a low level, and the marginal signal is at a low level.

Claim 26

A display device comprising a gate driver for supplying a corresponding signal to a plurality of scanning signal lines, a source driver for receiving an image signal, extracting an image data from the image signal and supplying the corresponding image data to a plurality of data signal lines, and display means for displaying the image data based on the signal, wherein the plurality of scanning signal lines is classified into a predetermined first group and a predetermine second group, the gate driver receives a control signal and further receives a sampling control signal, the gate driver supplies a corresponding first scanning pulse signal to the plurality of scanning signal lines when the control signal is in a first state, the gate driver supplies a corresponding second scanning pulse signal to scanning signal lines of the predetermined first group and supplies a non-selection signal to scanning signal lines of the predetermined second group based on the sampling control signal when the control signal is in a second state; and a width of the first scanning pulse signal is shorter than a width of the second scanning pulse signal.

Claim 27

A display device comprising a gate driver for supplying a corresponding signal to a plurality of scanning signal lines, a source driver for receiving an image signal, extracting an image data from the image signal and supplying the corresponding image data to a plurality of data signal lines, and display means for displaying the image data based on the signal, wherein the plurality of scanning signal lines is classified into a predetermined first group and a predetermine second group, the gate driver receives a control signal and further receives a sampling control signal, the gate driver supplies a corresponding first scanning pulse signal to the plurality of scanning signal lines when the control signal is in a first state, the gate driver supplies a corresponding second scanning pulse signal to scanning signal lines of the predetermined first group and supplies a non-selection signal to scanning signal lines of the predetermined second group based on the sampling control signal when the control signal is in a second state; and a width of the first scanning pulse signal is shorter than a width of the second scanning pulse signal.

Claim 28

A display device according to claim 16, wherein the gate driver includes a shift register array having a plurality of shift resisters corresponding to the scanning signal lines, and a logic circuit array having a plurality of logic circuits, The shift register array receives a start signal and a clock signal supplied from outside of the display device, supplies the start signal stored in a shift register to the logic circuit corresponding to the shift register based on the clock signal, and shifts the start signal to a shift register adjacent to the shift register in which the start signal is stored, and the logic circuit array supplies non-selection signals to the scanning signal lines of the second based on the sampling control signal, and generates the second scanning signal based on the start signal output from the shift register.

Claim 29

A display device comprising a gate driver for supplying a corresponding scanning signal to a plurality of scanning signal lines, a source driver for receiving an image signal, extracting a data from the image signal and supplying the corresponding data to a plurality of data signal lines, and display means for displaying the data based on the scanning signal, wherein the plurality of data signal lines is classified into a predetermined first group and a predetermined second group, the source driver receives a control signal and further receives a sampling control signal, the source driver supplies a corresponding first data pulse signal to the plurality of data signal lines when the control signal is in a first state, the source driver supplies a corresponding second data pulse signal to scanning signal lines of the predetermined first group and supplies a marginal signal to data signal lines of the predetermined second group based on the data control signal when the control signal is in a second state, and a width of the first data pulse signal is shorter than a width of the second data pulse signal.

Claim 30

A display device comprising a gate driver for supplying a corresponding scanning signal to a plurality of scanning signal lines, a source driver for receiving an image signal, extracting a data from the image signal and supplying the corresponding data to a plurality of data signal lines, and display means for displaying the data based on the scanning signal, wherein the plurality of data signal lines is classified into a predetermined first group and a predetermined second group, the source driver receives a control signal and further receives a sampling control signal, the source driver supplies a corresponding first data pulse signal to the plurality of data signal lines when the control signal is in a first state, the source driver supplies a corresponding second data pulse signal to scanning signal lines of the predetermined first group and supplies a marginal signal to data signal lines of the predetermined second group based on the data control signal when the control signal is in a second state, and a width of the first data pulse signal is shorter than a width of the second data pulse signal.

Claim 31

A display device according to claim 18, wherein the source driver includes a shift register array having a plurality of shift resisters corresponding to the data signal line, and a logic circuit array having a plurality of logic circuits, the shift register array receives a start signal and a clock signal supplied from outside of the display device, supplies the start signal stored in a shift register to the logic circuit corresponding to the shift register based on the clock signal, and shifts the start signal to a shift register adjacent to the shift register in which the start signal is stored, and the logic circuit array supplies the marginal signals to the data signal lines of the second based on the data control signal, and generates the second data signal based on the start signal output from the shift register.

Claim 32

A driving circuit for sequentially scanning a plurality of scanning signal lines, the driving circuit comprising a shift register having a plurality of unit registers and nodes, each of the plurality of unit registers being connected to the corresponding scanning signal line, a start signal input to a node being sequentially shifted to an adjacent unit register based on a standard signal when a control signal is at a first state such that a first portion of scanning signal lines are driven and the driving circuit operates in a first display mode; and the start signal input to another node being sequentially shifted to an adjacent unit register based on the standard signal when the control signal is at a second state such that a second portion of the scanning signal lines are driven and the driving circuit operates in a second display mode.

Claim 33

A driving circuit for sequentially scanning a plurality of scanning signal lines, the driving circuit comprising a shift register having a plurality of unit registers and nodes, each of the plurality of unit registers being connected to the corresponding scanning signal line, a start signal input to a node being sequentially shifted to an adjacent unit register based on a standard signal when a control signal is at a first state such that a first portion of scanning signal lines are driven and the driving circuit operates in a first display mode; and the start signal input to another node being sequentially shifted to an adjacent unit register based on the standard signal when the control signal is at a second state such that a second portion of the scanning signal lines are driven and the driving circuit operates in a second display mode.