Low voltage single ended dynamic sense amplifier

Claim 2

A sense amplifier circuit for sensing a state of a first node, the sense amplifier circuit comprising: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node, the discharge circuit comprising: a first field effect transistor (FET) having a drain, a source, and a gate, wherein the drain is coupled to the input node and the source is coupled to the first node; a noise margin circuit coupled to the first node, the noise margin circuit for charging the first node to a second voltage level that is greater than a first threshold voltage level of the first FET by a predetermined noise margin voltage, the noise margin circuit comprising: a second FET, configured as a diode, coupled between the first node and a first supply voltage for clamping the first node voltage level to the second voltage level; a threshold control circuit, the threshold control circuit comprising: a third FET having a drain, a source, and a gate wherein, the source is coupled to the first supply voltage and the gate is coupled to the first node; a fourth FET having a drain, a source, and a gate, wherein the source is coupled to a second supply voltage and the gate is coupled to a node located between the second FET and the first supply voltage, wherein the drain of the third FET and the drain of the fourth FET are coupled to each other, the output of the threshold control circuit, and to the gate of the first FET such that the gate of the first FET receives a discharge input voltage from the coupled drains of the third and fourth FETs so that the first FET couples the input node to the first node when the discharge input voltage reaches the first threshold voltage of the first FET.

Claim 3

A sense amplifier circuit for sensing a state of a first node, the sense amplifier circuit comprising: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node, the discharge circuit comprising: a first field effect transistor (FET) having a drain, a source, and a gate, wherein the drain is coupled to the input node and the source is coupled to the first node; a noise margin circuit coupled to the first node, the noise margin circuit comprising: a second FET having a drain, a source, and a gate wherein, the drain and the gate are coupled to a first supply voltage; a threshold control circuit, the threshold control circuit comprising: a third FET having a drain, a source, and a gate wherein, the source is coupled to the first supply voltage and the gate is coupled to the first node; a fifth FET, configured as a diode, coupled between the source of the second FET and the first node for clamping the first node voltage to a second voltage level; a fourth FET having a drain, a source, and a gate, wherein the source is coupled to a second supply voltage and the gate is coupled to a tap node located between the fifth FET and the source of the second FET, wherein the drain of the third FET and the drain of the fourth FET are coupled to each other, the output of the threshold control circuit, and to the gate of the first FET such that the gate of the first FET receives a discharge input voltage from the coupled drains of the third and fourth FETs such that the first FET couples the input node to the first node when the discharge input voltage reaches first threshold voltage of the first FET.

Claim 4

A sense amplifier circuit for sensing a state of a first node, the sense amplifier circuit comprising: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node, the discharge circuit comprising: a first field effect transistor (FET) having a drain, a source, and a gate, wherein the drain is coupled to the input node and the source is coupled to the first node; a noise margin circuit coupled to the first node, the noise margin circuit comprising: a second FET having a drain, a source, and a gate wherein, the drain and the gate are coupled to a first supply voltage; a threshold control circuit, the threshold control circuit comprising: a third FET having a drain, a source, and a gate wherein, the source is coupled to the first supply voltage and the gate is coupled to the first node; a fifth FET, configured as a diode, coupled between the source of the second FET and the first node for clamping the first node voltage to a second voltage level; a fourth FET having a drain, a source, and a gate, wherein the source is coupled to a second supply voltage and the gate is coupled to a tap node located between the fifth FET and the source of the second FET, wherein the drain of the third FET and the drain of the fourth FET are coupled to each other, the output of the threshold control circuit, and to the gate of the first FET such that the gate of the first FET receives a discharge input voltage from the coupled drains of the third and fourth FETs such that the first FET couples the input node to the first node when the discharge input voltage reaches first threshold voltage of the first FET.

Claim 5

A sense amplifier circuit for sensing a state of a first node, the sense amplifier circuit comprising: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node; a threshold control circuit coupled to the first node, wherein the threshold control circuit comprises: a first transistor having a first flow node, a second flow node, and a control node wherein, the second flow node is coupled to a first supply voltage and the control node is coupled to the first node; a second transistor having a first flow node, a second flow node and a control node, wherein the second flow node is coupled to a second supply voltage and the control node is coupled to a tap node located between a noise margin circuit and the first supply voltage, wherein the first flow node of the first transistor and the first flow node of the second transistor are coupled to each other and an input of the discharge circuit such that the input of the discharge circuit receives the discharge input voltage from the coupled first flow nodes of the first and second transistors and the discharge circuit couples the input node to the first node when the discharge input voltage from the threshold control circuit exceeds a first threshold voltage; and the noise margin circuit is coupled to the first node, the noise margin circuit for charging the first node to a second voltage level that is greater than the first threshold voltage by a predetermined noise margin voltage.

Claim 6

A sense amplifier circuit for sensing a state of a first node, the sense amplifier circuit comprising: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node; a threshold control circuit coupled to the first node, wherein the threshold control circuit comprises: a first transistor having a first flow node, a second flow node, and a control node wherein, the second flow node is coupled to a first supply voltage and the control node is coupled to the first node; a second transistor having a first flow node, a second flow node and a control node, wherein the second flow node is coupled to a second supply voltage and the control node is coupled to a tap node located between a noise margin circuit and the first supply voltage, wherein the first flow node of the first transistor and the first flow node of the second transistor are coupled to each other and an input of the discharge circuit such that the input of the discharge circuit receives the discharge input voltage from the coupled first flow nodes of the first and second transistors and the discharge circuit couples the input node to the first node when the discharge input voltage from the threshold control circuit exceeds a first threshold voltage; and the noise margin circuit is coupled to the first node, the noise margin circuit for charging the first node to a second voltage level that is greater than the first threshold voltage by a predetermined noise margin voltage.

Claim 7

The sense amplifier circuit of claim 3, wherein the discharge circuit comprises: a third transistor having a first flow node, a second flow node, and a control node, wherein the first flow node is coupled to the input node, the second flow node is coupled to the first node, and the control node is coupled to an output of the threshold control circuit to receive the discharge input voltage, the third transistor for coupling the input node to the first node when the discharge input voltage from the output of the threshold control circuit reaches the first threshold voltage of the third transistor.

Claim 8

The sense amplifier circuit of claim 4, wherein the noise margin circuit comprises: a diode coupled between the first node and a first supply voltage for clamping the first node voltage to a predetermined level.

Claim 9

The sense amplifier circuit of claim 5, wherein the second and third transistors are n-channel field effect transistors (FET's).

Claim 10

The sense amplifier circuit of claim 6, wherein the first node is a matchline of a comparator.

Claim 11

The sense amplifier circuit of claim 6, wherein the noise margin circuit comprises: a fourth transistor, having a first flow node, a second flow node, and a control node wherein, the first flow node and the control node are coupled to a first supply voltage.

Claim 12

A sense amplifier circuit for sensing a state of a first node, the sense amplifier circuit comprising: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node; a threshold control circuit coupled to the first node, wherein the threshold control circuit comprises: a first transistor having a first flow node, a second flow node, and a control node wherein, the second flow node is coupled to the first supply voltage and the control node is coupled to the first node; a diode, coupled between the second flow node of a second transistor and the first node, the diode for, in combination with the second transistor, clamping the first node voltage to a predetermined level; a third transistor having a first flow node, a second flow node and a control node, wherein the second flow node is coupled to a second supply voltage, the control node is coupled to a tap node located between the diode and the second flow node of the second transistor, wherein the first flow node of the first transistor and the first flow node of the third transistor are coupled to each other, the output of the threshold control circuit, and an input of the discharge circuit such that the input of the discharge circuit receives the discharge input voltage from the coupled first flow nodes of the first and third transistors and the discharge circuit couples the input node to the first node when the discharge input voltage from the threshold control circuit exceeds a first threshold voltage.

Claim 13

A sense amplifier circuit for sensing a state of a first node, the sense amplifier circuit comprising: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node; a threshold control circuit coupled to the first node, wherein the threshold control circuit comprises: a first transistor having a first flow node, a second flow node, and a control node wherein, the second flow node is coupled to the first supply voltage and the control node is coupled to the first node; a diode, coupled between the second flow node of a second transistor and the first node, the diode for, in combination with the second transistor, clamping the first node voltage to a predetermined level; a third transistor having a first flow node, a second flow node and a control node, wherein the second flow node is coupled to a second supply voltage, the control node is coupled to a tap node located between the diode and the second flow node of the second transistor, wherein the first flow node of the first transistor and the first flow node of the third transistor are coupled to each other, the output of the threshold control circuit, and an input of the discharge circuit such that the input of the discharge circuit receives the discharge input voltage from the coupled first flow nodes of the first and third transistors and the discharge circuit couples the input node to the first node when the discharge input voltage from the threshold control circuit exceeds a first threshold voltage.

Claim 14

The sense amplifier circuit of claim 9, wherein the second and third transistors are n-channel field effect transistors (FETs).

Claim 15

The sense amplifier circuit of claim 10, wherein the first node is a matchline of a comparator.

Claim 16

A computer system comprising: a memory; and a processor coupled to the memory, the processor including a register file having a memory location and a sense amplifier circuit coupled to the memory location via a first node, the sense amplifier circuit for determining a state of the memory location, the sense amplifier circuit including: output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node; a threshold control circuit coupled to the first node, wherein the threshold control circuit comprises: a first transistor having a first flow node, a second flow node, and a control node wherein, the second flow node is coupled to a first supply voltage and the control node is coupled to the first node; a second transistor having a first flow node, a second flow node and a control node, wherein the second flow node is coupled to a second supply voltage and the control node is coupled to a tap node located between a noise margin circuit and the first supply voltage, wherein the first flow node of the first transistor and the first flow node of the second transistor are coupled to each other and an input of the discharge circuit such that the input of the discharge circuit receives the discharge input voltage from the coupled first flow nodes of the first and second transistors and the discharge circuit couples the input node to the first node when the discharge input voltage from the threshold control circuit exceeds a first threshold voltage; and the noise margin circuit is coupled to the first node, the noise margin circuit for charging the first node to a second voltage level that is greater than the first threshold voltage by a predetermined noise margin voltage.

Claim 17

A computer system comprising: a memory; and a processor coupled to the memory, the processor including a register file having a memory location and a sense amplifier circuit coupled to the memory location via a first node, the sense amplifier circuit for determining a state of the memory location, the sense amplifier circuit including: output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node; a threshold control circuit coupled to the first node, wherein the threshold control circuit comprises: a first transistor having a first flow node, a second flow node, and a control node wherein, the second flow node is coupled to a first supply voltage and the control node is coupled to the first node; a second transistor having a first flow node, a second flow node and a control node, wherein the second flow node is coupled to a second supply voltage and the control node is coupled to a tap node located between a noise margin circuit and the first supply voltage, wherein the first flow node of the first transistor and the first flow node of the second transistor are coupled to each other and an input of the discharge circuit such that the input of the discharge circuit receives the discharge input voltage from the coupled first flow nodes of the first and second transistors and the discharge circuit couples the input node to the first node when the discharge input voltage from the threshold control circuit exceeds a first threshold voltage; and the noise margin circuit is coupled to the first node, the noise margin circuit for charging the first node to a second voltage level that is greater than the first threshold voltage by a predetermined noise margin voltage.

Claim 18

The computer system of claim 12, wherein the discharge circuit comprises: a third transistor having a first flow node, a second flow node, and a control node, wherein the first flow node is coupled to the input node, the second flow node is coupled to the first node, and the control node is coupled to an output of the threshold control circuit to receive the discharge input voltage, the third transistor for coupling the input node to the first node when the discharge input voltage from the output of the threshold control circuit reaches the first threshold voltage of the third transistor.

Claim 19

The computer system of claim 13, wherein the noise margin circuit comprises: a diode coupled between the first node and a first supply voltage for clamping the first node voltage to a predetermined level.

Claim 20

The computer system of claim 14, wherein the second and third transistors are n-channel field effect transistors (FET's).

Claim 21

The sense amplifier circuit of claim 15, wherein the first node is a matchline of a comparator.

Claim 22

The computer system of claim 12, wherein the noise margin circuit comprises: a fourth transistor, having a first flow node, a second flow node, and a control node wherein, the first flow node and the control node are coupled to a first supply voltage.

Claim 23

A computer system comprising: a memory; and a processor coupled to the memoroy, the processor including a register file having a memory location and a sense amplifier circuit coupled to the memory location via a first node, the sense amplifier circuit for determining a state of the memory location, the sense amplifier circuit including: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node; a threshold control circuit coupled to the first node, wherein the threshold control circuit comprises: a first transistor having a first flow node, a second flow node, and a control node wherein, the second flow node is coupled to the first supply voltage and the control node is coupled to the first node; a diode, coupled between the second flow node of a second transistor and the first node, the diode for, in combination with the second transistor, clamping the first node voltage to a predetermined level; a third transistor having a first flow node, a second flow node and a control node, wherein the second flow node is coupled to a second supply voltage, the control node is coupled to a tap node located between the diode and the second flow node of the second transistor, wherein the first flow node of the first transistor and the first flow node of the third transistor are coupled to each other, the output of the threshold control circuit, and an input of the discharge circuit such that the input of the discharge circuit receives the discharge input voltage from the coupled first flow nodes of the first and third transistors and the discharge circuit couples the input node to the first node when the discharge input voltage from the threshold control circuit exceeds a first threshold voltage.

Claim 24

A computer system comprising: a memory; and a processor coupled to the memoroy, the processor including a register file having a memory location and a sense amplifier circuit coupled to the memory location via a first node, the sense amplifier circuit for determining a state of the memory location, the sense amplifier circuit including: an output circuit having an input node and an output, the output for indicating a state of the first node in response to a voltage level at the first node; a precharge circuit coupled to the input node, the precharge circuit for charging the input node to a precharge voltage level; a discharge circuit coupled to the first node and the input node, the discharge circuit for discharging the input node from the precharge voltage level to the voltage level of the first node; a threshold control circuit coupled to the first node, wherein the threshold control circuit comprises: a first transistor having a first flow node, a second flow node, and a control node wherein, the second flow node is coupled to the first supply voltage and the control node is coupled to the first node; a diode, coupled between the second flow node of a second transistor and the first node, the diode for, in combination with the second transistor, clamping the first node voltage to a predetermined level; a third transistor having a first flow node, a second flow node and a control node, wherein the second flow node is coupled to a second supply voltage, the control node is coupled to a tap node located between the diode and the second flow node of the second transistor, wherein the first flow node of the first transistor and the first flow node of the third transistor are coupled to each other, the output of the threshold control circuit, and an input of the discharge circuit such that the input of the discharge circuit receives the discharge input voltage from the coupled first flow nodes of the first and third transistors and the discharge circuit couples the input node to the first node when the discharge input voltage from the threshold control circuit exceeds a first threshold voltage.

Claim 25

The computer system of claim 18, wherein the second and third transistors are n-channel field effect transistors (FETs).