Patent US5747378A successfully refreshed from Google Patents.
US5747378A
Expired / Lapsed
US
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Method of damage free doping for forming a dram memory cell
Assignee: Promos Technologies Inc
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Filing: 1997-05-27
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Granted: 1998-05-05
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Expires: 2017-05-27
Abstract
Abstract A method of damage-free doping for forming a dynamic random access memory cell is disclosed herein. A phosphoric silicate glass is deposited as a diffusion source. The phosphorous ions of phosphoric silicate glass can be diffused into a substrate to form the source/drain regions by a high temperature during a thermal annealing process. Next, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can reduce the damage of a dynamic random access memory.
Inventors
- 👤 Der-Tsyr Fan
- 👤 Chon-Shin Jou
- 👤 Ting-S. Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:06
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/013; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/144
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
164 words
A method of forming a dynamic random access memory comprising the steps of: forming a field oxide layer to define an active area; forming a gate oxide layer on a substrate; forming a polysilicon layer on said gate oxide layer; forming a photoresist layer on said polysilicon layer to define a gate electrode region; removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode; removing said photpresist layer; forming a dielectric layer on said gate electrode and said substrate; anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer; forming a phosphoric silicate glass on said gate electrode and said substrate; performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate; and performing thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode.
Claim 2
Independent Claim
164 words
A method of forming a dynamic random access memory comprising the steps of: forming a field oxide layer to define an active area; forming a gate oxide layer on a substrate; forming a polysilicon layer on said gate oxide layer; forming a photoresist layer on said polysilicon layer to define a gate electrode region; removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode; removing said photpresist layer; forming a dielectric layer on said gate electrode and said substrate; anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer; forming a phosphoric silicate glass on said gate electrode and said substrate; performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate; and performing thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode.
Claim 3
Dependent Claim
23 words
The method of claim 1, wherein said field oxide is formed to define said active area using the Local Oxidation of Silicon process.
Claim 4
Dependent Claim
25 words
The method of claim 1, wherein said gate oxide layer is formed to have a thickens in a range of about 40 to 200 angstroms.
Claim 5
Dependent Claim
22 words
The method of claim 1, wherein a thickness of said polysilicon layer is in a range of about 500 to 3000 angstroms.
Claim 6
Dependent Claim
24 words
The method of claim 1, wherein said dielectric layer is formed to have a thickens in a range of about 1000 to 3000 angstroms.
Claim 7
Dependent Claim
19 words
The method of claim 1, wherein said dielectric layer is phosphoric silicate glass formed by a chemical vapor deposition.
Claim 8
Dependent Claim
18 words
The method of claim 1, wherein said dielectric layer is silicon nitride formed by a chemical vapor deposition.
Claim 9
Dependent Claim
18 words
The method of claim 1, wherein said phosphoric silicate glass layer is formed by a chemical vapor deposition.
Claim 10
Dependent Claim
21 words
The method of claim 1, wherein said phosphoric silicate glass layer is in a range of about 200 to 2000 angstroms.
Claim 11
Dependent Claim
37 words
The method of claim 1, wherein the temperature to form said source and a drain regions is about 800° C. to 1100° C., the time of performing said annealing process being about 5 seconds to 1 hour.
Claim 12
Dependent Claim
28 words
The method of claim 1, wherein the impurity concentration of said source and a drain regions is about 10 18 atoms/cm 3 to 10 20 atoms/cm 3 .
Claim 13
Dependent Claim
19 words
The method of claim 1, wherein said thermal oxide layer is form by using a dry thermal oxidation process.
Claim 14
Dependent Claim
23 words
The method of claim 1, wherein the thickness of said thermal oxide layer is in a range of about 50 to 200 angstroms.
Claim 15
Dependent Claim
47 words
The method of claim 1, further comprising the steps after said source and said drain regions being formed: removing said phosphoric silicate glass layer by a dry etching process; performing a heavily doped process to MOS transistors of a periphery circuit in said dynamic random access memory.
Claim 16
Dependent Claim
50 words
The method of claim 1, further comprising the steps after said thermal oxide layer being formed: removing said phosphoric silicate glass layer by a wet etching process using 1% hydrofluoric acid solution; performing a heavily doped process to MOS transistors of a periphery circuit in said dynamic random access memory.
Claim 17
Independent Claim
260 words
A method of forming a dynamic random access memory comprising the steps of: forming a field oxide layer to define an active area; forming a gate oxide layer on a substrate; forming a polysilicon layer on said gate oxide layer; forming a photoresist layer on said polysilicon layer to define a gate electrode region; removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode; removing said photpresist layer; forming a dielectric layer on said gate electrode and said substrate; anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer; forming a phosphoric silicate glass on said gate electrode and said substrate, the thickness of said phosphoric silicate glass being in a range of about 200 to 2000 angstroms; performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate, the temperature of said annealing process being about 800° C. to 110° C., the time of said annealing process being about 5 seconds to 1 hour; performing a dry thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode, the thickness of said thermal oxide layer being in a range of about 50 to 200 angstroms; removing said phosphoric silicate glass layer by a wet etching process using 1% hydrofluoric acid solution; and performing a heavily doped process to MOS transistors of a periphery circuit in said dynamic random access memory.
Claim 18
Independent Claim
260 words
A method of forming a dynamic random access memory comprising the steps of: forming a field oxide layer to define an active area; forming a gate oxide layer on a substrate; forming a polysilicon layer on said gate oxide layer; forming a photoresist layer on said polysilicon layer to define a gate electrode region; removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode; removing said photpresist layer; forming a dielectric layer on said gate electrode and said substrate; anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer; forming a phosphoric silicate glass on said gate electrode and said substrate, the thickness of said phosphoric silicate glass being in a range of about 200 to 2000 angstroms; performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate, the temperature of said annealing process being about 800° C. to 110° C., the time of said annealing process being about 5 seconds to 1 hour; performing a dry thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode, the thickness of said thermal oxide layer being in a range of about 50 to 200 angstroms; removing said phosphoric silicate glass layer by a wet etching process using 1% hydrofluoric acid solution; and performing a heavily doped process to MOS transistors of a periphery circuit in said dynamic random access memory.
Claim 19
Dependent Claim
28 words
The method of claim 16, wherein the impurity concentration of said source and a drain regions is about 10 18 atoms/cm 3 to 10 20 atoms/cm 3 .
Claim 20
Independent Claim
255 words
A method of forming a dynamic random access memory comprising the steps of: forming a field oxide layer to define an active area; forming a gate oxide layer on a substrate; forming a polysilicon layer on said gate oxide layer; forming a photoresist layer on said polysilicon layer to define a gate electrode region; removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode; removing said photpresist layer; forming a dielectric layer on said gate electrode and said substrate; anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer; forming a phosphoric silicate glass on said gate electrode and said substrate, the thickness of said phosphoric silicate glass being in a range of about 200 to 2000 angstroms; performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate, the temperature of said annealing process being about 800° C. to 110° C., the time of said annealing process being about 5 seconds to 1 hour; removing said phosphoric silicate glass layer by a dry etching process; performing a heavily doped process to MOS transistors of a periphery circuit in said dynamic random access memory; and performing a dry thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode, the thickness of said thermal oxide layer being in a range of about 50 to 200 angstroms.
Claim 21
Independent Claim
255 words
A method of forming a dynamic random access memory comprising the steps of: forming a field oxide layer to define an active area; forming a gate oxide layer on a substrate; forming a polysilicon layer on said gate oxide layer; forming a photoresist layer on said polysilicon layer to define a gate electrode region; removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode; removing said photpresist layer; forming a dielectric layer on said gate electrode and said substrate; anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer; forming a phosphoric silicate glass on said gate electrode and said substrate, the thickness of said phosphoric silicate glass being in a range of about 200 to 2000 angstroms; performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate, the temperature of said annealing process being about 800° C. to 110° C., the time of said annealing process being about 5 seconds to 1 hour; removing said phosphoric silicate glass layer by a dry etching process; performing a heavily doped process to MOS transistors of a periphery circuit in said dynamic random access memory; and performing a dry thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode, the thickness of said thermal oxide layer being in a range of about 50 to 200 angstroms.
Claim 22
Dependent Claim
28 words
The method of claim 18, wherein the impurity concentration of said source and a drain regions is about 10 18 atoms/cm 3 to 10 20 atoms/cm 3 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |