Formation of a capacitor using a sacrificial etch stop

Claim 1

A method of forming a capacitor on a silicon wafer comprising: (a) providing a silicon wafer; (b) forming a first insulative layer on said silicon wafer; (c) forming a first conductive layer over said first insulative layer; (d) patterning said first conductive layer to form a first plate of said capacitor, said first plate having means for connection to external circuitry; (e) forming a second insulative layer over said first conductive layer; (f) depositing an etch-stop layer over said second insulative layer; (g) depositing a first photoresist layer over said wafer; (h) patterning said first photoresist layer to protect said first plate; (i) removing said etch-stop layer not protected by said first photoresist layer; (j) removing said first photoresist layer; (k) depositing a third insulative layer over said silicon wafer; (l) depositing a second photoresist layer over said silicon wafer; (m) patterning said second photoresist layer to define a second plate of said capacitor; (n) etching said third insulative layer with a unidirectional etching technique, thereby creating a first opening and exposing said etch-stop layer; (o) removing said second photoresist layer; (p) removing said etch-stop layer from said first opening; (q) depositing a second conductive layer over said silicon wafer; (r) etching said second conductive layer with a unidirectional etching technique, thereby leaving a plug of said second conductive layer in said first opening which comprises said second plate of said capacitor; (s) depositing a third conductive layer; and (t) patterning said third conductive layer thereby forming a connective wiring stripe to said plug.

Claim 2

A method of forming a capacitor on a silicon wafer comprising: (a) providing a silicon wafer; (b) forming a first insulative layer on said silicon wafer; (c) forming a first conductive layer over said first insulative layer; (d) patterning said first conductive layer to form a first plate of said capacitor, said first plate having means for connection to external circuitry; (e) forming a second insulative layer over said first conductive layer; (f) depositing an etch-stop layer over said second insulative layer; (g) depositing a first photoresist layer over said wafer; (h) patterning said first photoresist layer to protect said first plate; (i) removing said etch-stop layer not protected by said first photoresist layer; (j) removing said first photoresist layer; (k) depositing a third insulative layer over said silicon wafer; (l) depositing a second photoresist layer over said silicon wafer; (m) patterning said second photoresist layer to define a second plate of said capacitor; (n) etching said third insulative layer with a unidirectional etching technique, thereby creating a first opening and exposing said etch-stop layer; (o) removing said second photoresist layer; (p) removing said etch-stop layer from said first opening; (q) depositing a second conductive layer over said silicon wafer; (r) etching said second conductive layer with a unidirectional etching technique, thereby leaving a plug of said second conductive layer in said first opening which comprises said second plate of said capacitor; (s) depositing a third conductive layer; and (t) patterning said third conductive layer thereby forming a connective wiring stripe to said plug.

Claim 18

A method of forming an integrated circuit having semiconductor devices and capacitors comprising: (a) providing a silicon wafer having active areas enclosed by field isolation; (b) forming a first insulative layer over said active areas; (c) depositing a polysilicon layer over said silicon wafer; (d) patterning and etching said polysilicon layer by photolithographic techniques to form polysilicon gate electrodes for self-aligned polysilicon gate MOSFETs and first conductive plates of said capacitors, said first conductive plates having means for connection to said integrated circuit; (e) implanting ions thereby forming source and drain elements of said MOSFETs and increasing the conductivity of said polysilicon gate electrodes and said first conductive plates; (f) forming a second insulative layer over said polysilicon layer; (g) depositing an etch-stop layer over said second insulative layer; (h) depositing a first photoresist layer over said silicon wafer; (i) patterning said first photoresist layer to protect said etch-stop layer over said first conductive plates; (j) removing said etch-stop layer not protected by said first photoresist layer; (k) removing said first photoresist layer; (l) depositing a third insulative layer over said silicon wafer; (m) depositing a second photoresist layer over said silicon wafer; (n) patterning said second photoresist layer to define contact openings to said MOSFETs and second conductive plate openings to said capacitors; (o) etching said third insulative layer with a unidirectional etching technique, thereby forming contact openings to said MOSFETs and second conductive plate openings exposing said etch-stop layer at the bases thereof; (p) removing said second photoresist layer; (q) removing said etch-stop layer from said second conductive plate openings; (r) depositing a first conductive layer over said silicon wafer; (s) etching said first conductive layer with a unidirectional etching technique, thereby leaving isolated conductive plugs in said contact openings and said second conductive plate openings; (t) depositing a second conductive layer; (u) patterning said second conductive layer thereby forming connective wiring to said conductive plugs; (v) forming additional wiring levels for said integrated circuit as dictated by its design.

Claim 19

A method of forming an integrated circuit having semiconductor devices and capacitors comprising: (a) providing a silicon wafer having active areas enclosed by field isolation; (b) forming a first insulative layer over said active areas; (c) depositing a polysilicon layer over said silicon wafer; (d) patterning and etching said polysilicon layer by photolithographic techniques to form polysilicon gate electrodes for self-aligned polysilicon gate MOSFETs and first conductive plates of said capacitors, said first conductive plates having means for connection to said integrated circuit; (e) implanting ions thereby forming source and drain elements of said MOSFETs and increasing the conductivity of said polysilicon gate electrodes and said first conductive plates; (f) forming a second insulative layer over said polysilicon layer; (g) depositing an etch-stop layer over said second insulative layer; (h) depositing a first photoresist layer over said silicon wafer; (i) patterning said first photoresist layer to protect said etch-stop layer over said first conductive plates; (j) removing said etch-stop layer not protected by said first photoresist layer; (k) removing said first photoresist layer; (l) depositing a third insulative layer over said silicon wafer; (m) depositing a second photoresist layer over said silicon wafer; (n) patterning said second photoresist layer to define contact openings to said MOSFETs and second conductive plate openings to said capacitors; (o) etching said third insulative layer with a unidirectional etching technique, thereby forming contact openings to said MOSFETs and second conductive plate openings exposing said etch-stop layer at the bases thereof; (p) removing said second photoresist layer; (q) removing said etch-stop layer from said second conductive plate openings; (r) depositing a first conductive layer over said silicon wafer; (s) etching said first conductive layer with a unidirectional etching technique, thereby leaving isolated conductive plugs in said contact openings and said second conductive plate openings; (t) depositing a second conductive layer; (u) patterning said second conductive layer thereby forming connective wiring to said conductive plugs; (v) forming additional wiring levels for said integrated circuit as dictated by its design.