Method for making single transistor non-volatile electrically alterable semiconductor memory device

Claim 1

A method of forming an improved electrically programmable and erasable memory device on a semiconductor substrate having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a common line, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor having a source coupled to the common line, a drain coupled to an associated one of the plurality of column address lines, a control gate coupled to an associated one of the plurality of row address lines, the source and drain defining a channel region, a polycrystalline silicon floating gate located over a portion of the channel and a portion of the drain, said control gate located over a portion of the channel not occupied by the floating gate, and over a portion of the source, a gate insulating layer over said source, drain and channel region, and a tunneling insulator layer between said floating gate and said control gate, the improvement comprising forming said tunneling insulator layer by forming a polycrystalline silicon floating gate on the semiconductor substrate over said gate insulating layer, forming an SiO 2 , tunneling layer over said polycrystalline silicon floating gate by oxidizing said gate by wet oxidation; forming an interface SiN x O y layer between said floating gate and said SiO 2 tunneling layer by exposing the floating gate with said SiO 2 layer to N 2 O at a temperature, where x is in the range of about one (1) to two (2) and y is in the range of about two (2) to three (3) and forming a control gate over said SiO 2 tunneling layer with an insulating layer formed over control gate.

Claim 2

A method of forming an improved electrically programmable and erasable memory device on a semiconductor substrate having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a common line, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor having a source coupled to the common line, a drain coupled to an associated one of the plurality of column address lines, a control gate coupled to an associated one of the plurality of row address lines, the source and drain defining a channel region, a polycrystalline silicon floating gate located over a portion of the channel and a portion of the drain, said control gate located over a portion of the channel not occupied by the floating gate, and over a portion of the source, a gate insulating layer over said source, drain and channel region, and a tunneling insulator layer between said floating gate and said control gate, the improvement comprising forming said tunneling insulator layer by forming a polycrystalline silicon floating gate on the semiconductor substrate over said gate insulating layer, forming an SiO 2 , tunneling layer over said polycrystalline silicon floating gate by oxidizing said gate by wet oxidation; forming an interface SiN x O y layer between said floating gate and said SiO 2 tunneling layer by exposing the floating gate with said SiO 2 layer to N 2 O at a temperature, where x is in the range of about one (1) to two (2) and y is in the range of about two (2) to three (3) and forming a control gate over said SiO 2 tunneling layer with an insulating layer formed over control gate.