Selective call receivers with integer divide synthesizers for achieving fast-lock time

Claim 2

A selective call receiver for receiving and transmitting paging signals, comprising: a transceiver having an integer divide synthesizer for achieving a fast lock time, the transceiver comprising: a reference oscillator for generating a low frequency reference signal in a direct injection path for deriving a time base signal; a modulator coupled in the direct injection path for modulating the low frequency reference signal to generate a modulated reference signal; a phase locked offset loop coupled to the direct injection path for dividing the time base signal to a low frequency signal derived from the reference signal to generate a fast lock time offset loop signal, the phase locked loop further comprises an integer divider that generates a low current drain feed back loop signal; a multiplier coupled to the modulator for multiplying the modulated reference signal; and a mixer coupled to the multiplier for receiving the modulated reference signal in the direct injection path and an output signal from the phase locked offset loop to generate an agile high frequency first local oscillator output signal and a modulated transmit carrier.

Claim 3

The selective call receiver according to claim 1 wherein the phase locked offset loop generates the low frequency signal derived from the reference signal before the reference signal is modulated.

Claim 4

The selective call receiver according to claim 1 wherein the phase locked offset loop comprises a programmable divider for switching between at least two frequencies.

Claim 5

An integer divide synthesizer for achieving a fast lock time, comprising: a reference oscillator for generating a low frequency reference signal in a direct injection path for deriving a time base signal; a modulator coupled in the direct injection path for modulating the low frequency reference signal to generate a modulated reference signal; a phase locked offset loop coupled to the direct injection path for dividing the time base signal to a low frequency signal derived from the reference signal to generate a fast lock time offset loop signal, the phase locked loop further comprises an integer divider that generates a low current drain feed back loop signal; a multiplier coupled to the modulator for multiplying the modulated reference signal; and a mixer coupled to the multiplier for receiving the modulated reference signal in the direct injection path and an output signal from the phase locked offset loop for generating an agile high frequency first local oscillator output signal and a modulated transmit carrier.

Claim 6

An integer divide synthesizer for achieving a fast lock time, comprising: a reference oscillator for generating a low frequency reference signal in a direct injection path for deriving a time base signal; a modulator coupled in the direct injection path for modulating the low frequency reference signal to generate a modulated reference signal; a phase locked offset loop coupled to the direct injection path for dividing the time base signal to a low frequency signal derived from the reference signal to generate a fast lock time offset loop signal, the phase locked loop further comprises an integer divider that generates a low current drain feed back loop signal; a multiplier coupled to the modulator for multiplying the modulated reference signal; and a mixer coupled to the multiplier for receiving the modulated reference signal in the direct injection path and an output signal from the phase locked offset loop for generating an agile high frequency first local oscillator output signal and a modulated transmit carrier.

Claim 7

The low frequency integer divide synthesizer according to claim 4 wherein the phase locked offset loop generates the low frequency signal derived from the reference signal before the reference signal is modulated.

Claim 8

The low frequency integer divide synthesizer according to claim 4 wherein the phase locked offset loop comprises a programmable divider for switching between at least two frequencies.

Claim 9

A transceiver for receiving and transmitting a signal, comprising: a programmable offset loop for switching an unmodulated signal between at least two frequencies, the programmable offset loop comprises: a low current integer divide PLL coupled to a reference oscillator signal; an integer divide synthesizer for achieving a fast lock time comprising a reference oscillator for generating a low frequency reference signal in a direct injection path for deriving a time base signal; a modulator coupled in the direct injection path for modulating the low frequency reference signal to generated a modulated reference signal; a phase locked offset loop coupled to the direct injection path for dividing the time base signal to a signal derived from the reference signal to generate a fast lock time offset loop signal, the phase locked loop further comprises an integer divider that generates a low current drain feed back loop signal; a multiplier coupled to the modulator for multiplying the modulated reference signal; and a mixer coupled to the multiplier receiving the modulated reference signal in the direct injection path and an output signal from the phase locked offset loop to generate an agile high frequency first local oscillator output signal.

Claim 10

A transceiver for receiving and transmitting a signal, comprising: a programmable offset loop for switching an unmodulated signal between at least two frequencies, the programmable offset loop comprises: a low current integer divide PLL coupled to a reference oscillator signal; an integer divide synthesizer for achieving a fast lock time comprising a reference oscillator for generating a low frequency reference signal in a direct injection path for deriving a time base signal; a modulator coupled in the direct injection path for modulating the low frequency reference signal to generated a modulated reference signal; a phase locked offset loop coupled to the direct injection path for dividing the time base signal to a signal derived from the reference signal to generate a fast lock time offset loop signal, the phase locked loop further comprises an integer divider that generates a low current drain feed back loop signal; a multiplier coupled to the modulator for multiplying the modulated reference signal; and a mixer coupled to the multiplier receiving the modulated reference signal in the direct injection path and an output signal from the phase locked offset loop to generate an agile high frequency first local oscillator output signal.

Claim 11

In transceiver, a method for obtaining a fast lock time signal, comprising the steps of: generating a low frequency reference signal for deriving a time base signal; dividing the time base signal; modulating the low frequency reference signal for generating a modulated reference signal; multiplying the modulated reference signal; dividing the time base signal to a low frequency offset loop signal for generating a fast lock time offset loop signal; generating a low current drain feed back loop signal with a phase lock loop having an integer divider; and mixing the modulated reference signal with the low frequency offset loop signal for generating an agile high frequency first local oscillator and modulated transmit signal.

Claim 12

In transceiver, a method for obtaining a fast lock time signal, comprising the steps of: generating a low frequency reference signal for deriving a time base signal; dividing the time base signal; modulating the low frequency reference signal for generating a modulated reference signal; multiplying the modulated reference signal; dividing the time base signal to a low frequency offset loop signal for generating a fast lock time offset loop signal; generating a low current drain feed back loop signal with a phase lock loop having an integer divider; and mixing the modulated reference signal with the low frequency offset loop signal for generating an agile high frequency first local oscillator and modulated transmit signal.

Claim 13

The method according to claim 8 wherein the step of dividing the time base signal further comprising dividing the time base signal to generate at least an DSP clock loop.