Circuit for generating a pulse signal to drive a pulse latch

Claim 2

A pulse generating circuit for generating a pulse signal used to drive a pulse latch, the circuit comprising: a first portion including, a logical AND device to receive a control signal and a first signal, a first transistor having a first terminal to be coupled to a voltage source, a second terminal coupled to the first signal, and a gate terminal coupled to the control signal, wherein the first portion is operative to generate a rising edge of the pulse signal in response to the control signal transitioning to a first state, and wherein the first portion is also operative to provide the pulse signal to the pulse latch; and a second portion, coupled to the first portion, operative to receive the rising edge of the pulse signal and to cause the first signal to transition to a second state in response to the rising edge of the pulse signal, the first portion operative to generate a falling edge of the pulse signal in response to the first signal transitioning to the second state.

Claim 3

The pulse generating circuit of claim 1, further comprising a storage portion coupled to the first portion and the second portion.

Claim 4

The pulse generating circuit of claim 2, wherein the storage portion comprises: a first inverter having an input and an output; and a second inverter having an input and an output, wherein the output of the second inverter is coupled to the input of the first inverter and the output of the first inverter is coupled to the input of the second inverter.

Claim 5

The pulse generating circuit of claim 1, wherein the second portion comprises: a second transistor having a first terminal coupled to a ground, a second terminal coupled to the first signal, and a gate terminal coupled to an output of the logical AND device.

Claim 6

A pulse generating circuit for generating a pulse signal used to drive a pulse latch, the circuit comprising: a first transistor having a first terminal coupled to a voltage, a gate terminal coupled to a control signal, and a second terminal coupled to a node; a second transistor having a first terminal coupled to the node, a second terminal coupled to a ground, and a gate terminal, the first and second transistors operating together to generate a first signal at the node; and a logical AND device which outputs the pulse signal to the pulse latch, the logical AND device having a first input coupled to the control signal, a second input coupled to the second terminal of the first transistor, and an output coupled to the gate terminal of the second transistor.

Claim 7

A pulse generating circuit for generating a pulse signal used to drive a pulse latch, the circuit comprising: a first transistor having a first terminal coupled to a voltage, a gate terminal coupled to a control signal, and a second terminal coupled to a node; a second transistor having a first terminal coupled to the node, a second terminal coupled to a ground, and a gate terminal, the first and second transistors operating together to generate a first signal at the node; and a logical AND device which outputs the pulse signal to the pulse latch, the logical AND device having a first input coupled to the control signal, a second input coupled to the second terminal of the first transistor, and an output coupled to the gate terminal of the second transistor.

Claim 8

The pulse generating circuit of claim 5, wherein the first transistor is a p-channel transistor.

Claim 9

The pulse generating circuit of claim 5, wherein the second transistor is an n-channel transistor.

Claim 10

The pulse generating circuit of claim 5, wherein the control signal is a clock signal.

Claim 11

The pulse generating circuit of claim 5, wherein the logical AND device is a logical AND gate.

Claim 12

The pulse generating circuit of claim 5, further comprising a storage device coupled to the second terminal of the first transistor.

Claim 13

The pulse generating circuit of claim 10, wherein the storage device comprises: a first inverter having an input and an output; and a second inverter having an input and an output, wherein the output of the second inverter is coupled to the input of the first inverter and the output of the first inverter is coupled to the input of the second inverter.

Claim 14

The pulse generating circuit of claim 11, wherein the output of the second inverter is also coupled to the second terminal of the first transistor.

Claim 15

The pulse generating circuit of claim 5, wherein the logical AND device comprises: a logical NAND gate having an output; and an inverter having an input coupled to the output of the logical NAND gate.

Claim 16

The pulse generating circuit of claim 13, further comprising an inverted pulse output coupled to the output of the logical NAND gate.

Claim 17

A pulse generating circuit for generating a pulse signal used to drive a pulse latch, the circuit comprising: first means for generating a rising edge of the pulse signal, the first means including a logical AND device configured to receive a control signal and a first signal, and a first transistor having a first terminal coupled to a voltage source, a second terminal coupled to the first signal, and a gate terminal coupled to the control signal, wherein the first means is for generating the rising edge of the pulse signal responsive to the control signal transitioning to a first state, the first means also for providing the pulse signal to the pulse latch; and second means, coupled to the first means, for receiving the rising edge of the pulse signal, wherein the second means is also for causing the first signal to transition to a second state in response to the rising edge of the pulse signal, and the first means is also for generating a falling edge of the pulse signal responsive to the first signal transitioning to the second state.

Claim 18

A pulse generating circuit for generating a pulse signal used to drive a pulse latch, the circuit comprising: first means for generating a rising edge of the pulse signal, the first means including a logical AND device configured to receive a control signal and a first signal, and a first transistor having a first terminal coupled to a voltage source, a second terminal coupled to the first signal, and a gate terminal coupled to the control signal, wherein the first means is for generating the rising edge of the pulse signal responsive to the control signal transitioning to a first state, the first means also for providing the pulse signal to the pulse latch; and second means, coupled to the first means, for receiving the rising edge of the pulse signal, wherein the second means is also for causing the first signal to transition to a second state in response to the rising edge of the pulse signal, and the first means is also for generating a falling edge of the pulse signal responsive to the first signal transitioning to the second state.

Claim 19

The pulse generating circuit of claim 15, further comprising a storage means coupled to the first means and the second means.

Claim 20

The pulse generating circuit of claim 16, wherein the storage means comprises: a first inverter having an input and an output; and a second inverter having an input and an output, wherein the output of the second inverter is coupled to the input of the first inverter and the output of the first inverter is coupled to the input of the second inverter.

Claim 21

The pulse generating circuit of claim 15, wherein the second means comprises: a second transistor having a first terminal coupled to a ground, a second terminal coupled to the first signal, and a gate terminal coupled to an output of the logical AND device.