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US5741733A
Expired / Lapsed
US
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Method for the production of a three-dimensional circuit arrangement
Assignee: Infineon Technologies AG
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Filing: 1995-01-12
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Granted: 1998-04-21
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Expires: 2015-01-12
Abstract
Abstract To produce a three-dimensional circuit arrangement, a first substrate (1) is thinned, stacked onto a second substrate (2) and fixedly connected to the latter. The first substrate (1) and the second substrate (2) in this case each comprise circuit structures (12, 22) and metallization planes (13, 23). At least one first contact hole (16) and one second contact hole (4) are opened, which reach the metallization plane (13, 23) in the first substrate (1) and second substrate (2), respectively, the second contact hole (4) passing through the first substrate (1). The metallization planes (13, 23) of the two substrates (1, 2) are electrically connected to one another via a conductive layer (7).
Inventors
- 👤 Emmerich Bertagnolli
- 👤 Helmut Klose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:35
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10W20/0234; H10W20/0253; H10W20/20; H10W20/211; H10W20/212; H10W20/2125; H10W20/213; H10W20/2134; H10W99/00
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
284 words
A method for producing a three-dimensional circuit arrangement, comprising the steps of: connecting a first substrate, which comprises, in a region of a first main area, at least one first circuit structure, a first metallization plane and a first passivation layer which covers said first metallization plane, to an auxiliary substrate via a first adhesion layer which is applied to said first main area, thinning said first substrate at a second main area opposite to said first main area, providing a second substrate, which comprises, in a region of a third main area, at least one second circuit structure, a second metallization plane and a second passivation layer which covers said second metallization plane, with a second adhesion layer on said third main area, joining said first substrate and said second substrate together in such a way that said second main area of said first substrate adjoins said second adhesion layer on said second substrate, and that said first substrate and said second substrate are fixedly connected via said second adhesion layer, opening a first contact hole from said first main area to said first metallization plane, opening, after removal of said auxiliary substrate and of said first adhesion layer, at least one second contact hole to said second metallization plane starting from said first main area, said opening step of said at least one second contact hole including etching said at least one second contact hole through material of said first substrate, said opening step of said at least one second contact hole being performed after said joining step, producing a conductive layer on said first main area and electrically connecting said first metallization plane and said second metallization plane to one another.
Claim 2
Independent Claim
284 words
A method for producing a three-dimensional circuit arrangement, comprising the steps of: connecting a first substrate, which comprises, in a region of a first main area, at least one first circuit structure, a first metallization plane and a first passivation layer which covers said first metallization plane, to an auxiliary substrate via a first adhesion layer which is applied to said first main area, thinning said first substrate at a second main area opposite to said first main area, providing a second substrate, which comprises, in a region of a third main area, at least one second circuit structure, a second metallization plane and a second passivation layer which covers said second metallization plane, with a second adhesion layer on said third main area, joining said first substrate and said second substrate together in such a way that said second main area of said first substrate adjoins said second adhesion layer on said second substrate, and that said first substrate and said second substrate are fixedly connected via said second adhesion layer, opening a first contact hole from said first main area to said first metallization plane, opening, after removal of said auxiliary substrate and of said first adhesion layer, at least one second contact hole to said second metallization plane starting from said first main area, said opening step of said at least one second contact hole including etching said at least one second contact hole through material of said first substrate, said opening step of said at least one second contact hole being performed after said joining step, producing a conductive layer on said first main area and electrically connecting said first metallization plane and said second metallization plane to one another.
Claim 3
Dependent Claim
31 words
A method as claimed in claim 1, further comprising the step of: producing side insulation on side walls of at least said second contact hole prior to production of conductive layer.
Claim 4
Dependent Claim
48 words
A method as claimed in claim 1, further comprising the steps of: providing said first substrate and said second substrate with alignment marks; and aligning said first and second substrates with one another using infrared transmitted light when said first substrate and said second substrate are joined together.
Claim 5
Dependent Claim
18 words
A method as claimed in claim 1, further comprising the step of: thinning said first substrate by grinding.
Claim 6
Dependent Claim
61 words
A method as claimed in claim 4, wherein at least said first substrate is an SOI substrate which comprises a monocrystalline silicon layer, a buried oxide layer and a silicon wafer, and further comprising the steps of: removing said silicon wafer during thinning of said first substrate, establishing said first circuit structure in said monocrystalline silicon layer of said SOI substrate.
Claim 7
Dependent Claim
25 words
A method as claimed in claim 1, further comprising the step of: applying a further passivation layer to a whole area of said conductive layer.
Claim 8
Dependent Claim
25 words
A method as claimed in claim 1, further comprising the step of; providing further metallization planes in said first substrate, under said first metallization plane.
Claim 9
Dependent Claim
49 words
A method as claimed in claim 1, wherein said first adhesion layer comprises an adhesive selected from the group consisting of a polyimide adhesive and a polyacrylate adhesive and wherein said first adhesiveU is removed by a removal method selected from O 2 plasma methods or wet-chemical removal methods.
Claim 10
Dependent Claim
35 words
A method as claimed in one of claim 1, wherein said second adhesion layer is a polyimide adhesive which is cured by polymerization after said first substrate and said second substrate have been joined together.
Claim 11
Dependent Claim
32 words
A method as claimed in claim 1, wherein said second contact hole is opened using combined etching which comprises at least isotropic etching using HNO3/HF and anisotropic etching using an HBr plasma.
Claim 12
Dependent Claim
22 words
A method as claimed in claim 1, wherein said second contact hole is opened using anisotropic etching using CHF3 and HBr plasmas.
Claim 13
Dependent Claim
18 words
A method as claimed in claim 1, further comprising the step of: thinning said first substrate by etching.
Claim 14
Dependent Claim
25 words
A method as claimed in claim 1, further comprising the step of; providing further metallization planes in said second substrate under said second metallization plane.
Claim 15
Independent Claim
288 words
A method for producing a three-dimensional circuit arrangement, comprising the steps of: connecting a first substrate of silicon, which comprises, in a region of a first main area, at least one first circuit structure, a first metallization plane and a first passivation layer which covers said first metallization plane, to an auxiliary substrate via a first adhesion layer which is applied to said first main area, thinning said first substrate at a second main area opposite to said first main area, providing a second substrate of silicon, which comprises, in a region of a third main area, at least one second circuit structure, a second metallization plane and a second passivation layer which covers said second metallization plane, with a second adhesion layer on said third main area, joining said first substrate and said second substrate together in such a way that said second main area of said first substrate adjoins said second adhesion layer on said second substrate, and that said first substrate and said second substrate are fixedly connected via said second adhesion layer, opening a first contact hole from said first main area to said first metallization plane, opening, after removal of said auxiliary substrate and of said first adhesion layer, at least one second contact hole to said second metallization plane starting from said first main area, said opening step of said at least one second contact hole including etching said at least one second contact hole through material of said first substrate, said opening step of said at least one second contact hole being performed after said joining step, producing a conductive layer on said first main area and electrically connecting said first metallization plane and said second metallization plane to one another.
Claim 16
Independent Claim
288 words
A method for producing a three-dimensional circuit arrangement, comprising the steps of: connecting a first substrate of silicon, which comprises, in a region of a first main area, at least one first circuit structure, a first metallization plane and a first passivation layer which covers said first metallization plane, to an auxiliary substrate via a first adhesion layer which is applied to said first main area, thinning said first substrate at a second main area opposite to said first main area, providing a second substrate of silicon, which comprises, in a region of a third main area, at least one second circuit structure, a second metallization plane and a second passivation layer which covers said second metallization plane, with a second adhesion layer on said third main area, joining said first substrate and said second substrate together in such a way that said second main area of said first substrate adjoins said second adhesion layer on said second substrate, and that said first substrate and said second substrate are fixedly connected via said second adhesion layer, opening a first contact hole from said first main area to said first metallization plane, opening, after removal of said auxiliary substrate and of said first adhesion layer, at least one second contact hole to said second metallization plane starting from said first main area, said opening step of said at least one second contact hole including etching said at least one second contact hole through material of said first substrate, said opening step of said at least one second contact hole being performed after said joining step, producing a conductive layer on said first main area and electrically connecting said first metallization plane and said second metallization plane to one another.
Claim 17
Dependent Claim
31 words
A method as claimed in claim 14, further comprising the step of: producing side insulation on side walls of at least said second contact hole prior to production of conductive layer.
Claim 18
Dependent Claim
48 words
A method as claimed in claim 14, further comprising the steps of: providing said first substrate and said second substrate with alignment marks; and aligning said first and second substrates with one another using infrared transmitted light when said first substrate and said second substrate are joined together.
Claim 19
Dependent Claim
18 words
A method as claimed in claim 14, further comprising the step of: thinning said first substrate by grinding.
Claim 20
Dependent Claim
61 words
A method as claimed in claim 17, wherein at least said first substrate is an SOI substrate which comprises a monocrystalline silicon layer, a buried SiO2 layer and a silicon wafer, and further comprising the steps of: removing said silicon wafer during thinning of said first substrate, establishing said first circuit structure in said monocrystalline silicon layer of said SOI substrate.
Claim 21
Dependent Claim
25 words
A method as claimed in claim 14, further comprising the step of: applying a further passivation layer to a whole area of said conductive layer.
Claim 22
Dependent Claim
25 words
A method as claimed in claim 14, further comprising the step of: providing further metallization planes in said first substrate, under said first metallization plane.
Claim 23
Dependent Claim
49 words
A method as claimed in claim 14, wherein said first adhesion layer comprises an adhesive selected from the group consisting of a polyimide adhesive and a polyacrylate adhesive and wherein said first adhesive is removed by a removal method selected from O 2 plasma methods or wet-chemical removal methods.
Claim 24
Dependent Claim
35 words
A method as claimed in one of claim 14, wherein said second adhesion layer is a polyimide adhesive which is cured by polymerization after said first substrate and said second substrate have been joined together.
Claim 25
Dependent Claim
34 words
A method as claimed in claim 14, wherein said second contact hole is opened using combined etching which comprises at least isotropic etching using HNO 3 /HF and anisotropic etching using an HBr plasma.
Claim 26
Dependent Claim
23 words
A method as claimed in claim 14, wherein said second contact hole is opened using anisotropic etching using CHF 3 and HBr plasmas.
Claim 27
Dependent Claim
18 words
A method as claimed in claim 14, further comprising the step of: thinning said first substrate by etching.
Claim 28
Dependent Claim
25 words
A method as claimed in claim 14, further comprising the step of: providing further metallization planes in said second substrate under said second metallization plane.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-20 | 2001-10-20 | 2002-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-20 | 2005-10-20 | 2006-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-20 | 2009-10-20 | 2010-04-21 | $7700.00 | Window Closed / Lapsed |