Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a row-system circuit for receiving a first power from a power supply and operable in accordance with a row address strobe signal; a column-system circuit operable in accordance with a column address strobe signal; and a switch circuit, connected to said column-system circuit, for receiving said first power from said power supply and supplying said first power to said column-system circuit in an active mode and for shutting of the supply of the first power to said column-system circuit in a standby mode.

Claim 3

The semiconductor memory device according to claim 1, further comprising: a first power line connected between said power supply and said row-system circuit and also connected to said switch circuit; and a second power line connected between said switch circuit and said column-system circuit.

Claim 4

The semiconductor memory device according to claim 1, wherein said first power has a high potential and said second power has a ground potential.

Claim 5

The semiconductor memory device according to claim 2, wherein said switch circuit includes: a self-refresh entry circuit, connected to said first power line, for receiving said row address strobe signal and outputting an entry signal indicative of either said active mode or a self-refresh mode based on said row address strobe signal; and a transistor, connected to said first and second power lines, for permitting supply of said first power to said second power line from said first power line in response to said entry signal indicative of said active mode and for inhibiting supply of said first power and producing said second power in response to said entry signal indicative of said self-refresh mode.

Claim 6

The semiconductor memory device according to claim 4, wherein said transistor is a P channel MOS transistor.

Claim 7

The semiconductor memory device according to claim 4, wherein said switch circuit includes a level converter, connected between said self-refresh entry circuit and said transistor, for receiving said entry signal indicative of said self-refresh mode and converting a level of said received entry signal to a voltage level higher than that of said first power.

Claim 8

A semiconductor memory device comprising: a row-system circuit for receiving a first power from a power supply and operable in accordance with a row address strobe signal; a column-system circuit operable in accordance with a column address strobe signal; a switch circuit, connected to said column-system circuit, for receiving said first power from said power supply and supplying said first power to said column-system circuit in an active mode and for producing a second power lower than said first power and supplying said second power to said column-system circuit in a standby mode; a first power line connected between said power supply and said row-system circuit and also connected to said switch circuit; and a second power line connected between said switch circuit and said column-system circuit, wherein said switch circuit includes an active entry circuit, connected to said first power line, for receiving said row address strobe signal and outputting an entry signal indicative of either said active mode or said standby mode based on said row address strobe signal, a first transistor, connected between said first and second power lines, for permitting supply of said first power to said second power line from said first power line in response to said entry signal indicative of said active mode, and a second transistor, connected between said first and second power lines, for producing said second power lower than said first power in response to said entry signal indicative of said standby mode.

Claim 9

A semiconductor memory device comprising: a row-system circuit for receiving a first power from a power supply and operable in accordance with a row address strobe signal; a column-system circuit operable in accordance with a column address strobe signal; a switch circuit, connected to said column-system circuit, for receiving said first power from said power supply and supplying said first power to said column-system circuit in an active mode and for producing a second power lower than said first power and supplying said second power to said column-system circuit in a standby mode; a first power line connected between said power supply and said row-system circuit and also connected to said switch circuit; and a second power line connected between said switch circuit and said column-system circuit, wherein said switch circuit includes an active entry circuit, connected to said first power line, for receiving said row address strobe signal and outputting an entry signal indicative of either said active mode or said standby mode based on said row address strobe signal, a first transistor, connected between said first and second power lines, for permitting supply of said first power to said second power line from said first power line in response to said entry signal indicative of said active mode, and a second transistor, connected between said first and second power lines, for producing said second power lower than said first power in response to said entry signal indicative of said standby mode.

Claim 10

The semiconductor memory device according to claim 7, wherein said first transistor is a P channel MOS transistor and said second transistor is an N channel MOS transistor.

Claim 11

The semiconductor memory device according to claim 7, wherein said first power has a high potential and said second power has a potential lower than said high potential by a threshold value of said second transistor.

Claim 12

A semiconductor memory device comprising: a row-system circuit receiving a power via a power supply line and operating in response to a row address strobe signal; a column-system circuit operating in response to a column address strobe signal; and a switch circuit connected between said power supply line and a power source node of said column-system circuit, the switch circuit turning on during a normal mode to supply said power to said column-system circuit and the switch circuit turning off during a refresh mode to shut off the supply of power to said column-system circuit.

Claim 13

A semiconductor memory device comprising: a row-system circuit receiving a power via a power supply line and operating in response to a row address strobe signal; a column-system circuit operating in response to a column address strobe signal; and a switch circuit connected between said power supply line and a power source node of said column-system circuit, the switch circuit turning on during a normal mode to supply said power to said column-system circuit and the switch circuit turning off during a refresh mode to shut off the supply of power to said column-system circuit.