US5737628A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprocessor computer system with interleaved processing element nodes
Assignee: Morgan Stanley and Co LLC
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Filing: 1996-06-12
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Granted: 1998-04-07
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Expires: 2016-06-12
Abstract
Abstract A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
Inventors
- 👤 Mark S. Birrittella
- 👤 Richard E. Kessler
- 👤 Steven M. Oberlin
- 👤 Randal S. Passint
- 👤 Greg Thorson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:20
CPC Classifications
H; H04; H04L; H04L45/00; H04L45/02; H04L45/06; G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17356; G06F15/17368; G06F15/17381; H04L45/10; H04L49/00; H04L49/10; H04L49/101; H04L49/20; H04L49/205; H04L49/25; H04L49/251
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
132 words
A multiprocessor computer system comprising: a plurality of processing element nodes capable of executing more than one instruction simultaneously, each node including a processing element having a processor and a local memory, wherein globally addressable portions of local memory of each processing element form a distributed memory; an interconnection network connecting together the processing element nodes in an n-dimensional topology, wherein n is at least two, the network comprising internode communication paths connecting each of the plurality of processing element nodes to adjacent processing element nodes, wherein the maximum interconnection distance between the processing element nodes is minimized by interleaving selected ones of the plurality of processing element nodes in at least one of the n dimensions; and a network router for transmitting messages between processing element nodes via the interconnection network.
Claim 2
Dependent Claim
132 words
A multiprocessor computer system comprising: a plurality of processing element nodes capable of executing more than one instruction simultaneously, each node including a processing element having a processor and a local memory, wherein globally addressable portions of local memory of each processing element form a distributed memory; an interconnection network connecting together the processing element nodes in an n-dimensional topology, wherein n is at least two, the network comprising internode communication paths connecting each of the plurality of processing element nodes to adjacent processing element nodes, wherein the maximum interconnection distance between the processing element nodes is minimized by interleaving selected ones of the plurality of processing element nodes in at least one of the n dimensions; and a network router for transmitting messages between processing element nodes via the interconnection network.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |