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US5737613A
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Method of operating microcomputer to minimize power dissipation while accessing slow memory
Assignee: Individual
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Filing: 1995-03-10
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Granted: 1998-04-07
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Expires: 2015-03-10
Abstract
Abstract A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a first frequency, a second memory operable at a lower second frequency, including operating the entire CMOS microcomputer at the first frequency while accessing the first memory, causing the CMOS microcomputer to dissipate power at a first level, determining from a user program currently being executed that it is necessary to access the second memory, and operating the entire CMOS microcomputer at the lower second frequency while accessing the second memory to cause the CMOS microcomputer to dissipate power at a second level which is lower than the first level. The user program is executed to set a first speed control bit to a first level indicating that the second memory is to be accessed at the second frequency, and the second frequency is selected as a system clock frequency for the entire CMOS microcomputer in response to the first level of the first speed control bit. The second frequency is selected as the system clock frequency in response to a coincidence of one of a plurality of speed control bits and a corresponding one of a plurality of chip control outputs.
Inventors
- 👤 William D. Mensch, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:23
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/04; G06F1/08; G06F1/3287; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814; G11; G11C; G11C5/00; G11C5/02; G11C5/025; H; H03; H03H; H03H21/00; H03H21/0012; H03H2021/007; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
135 words
A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a first frequency, a second memory operable at a second frequency, the first frequency being higher than the second frequency, the method comprising the steps of: (a) operating the entire CMOS microcomputer at the first frequency while accessing the first memory, causing the CMOS microcomputer to dissipate power at a first level; (b) determining from a user program currently being executed that it is necessary to access the second memory; and (c) in response to the determining of step (b), operating the entire CMOS microcomputer at the second frequency while accessing the second memory, causing the CMOS microcomputer to dissipate power at a second level which is lower than the first level.
Claim 2
Independent Claim
135 words
A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a first frequency, a second memory operable at a second frequency, the first frequency being higher than the second frequency, the method comprising the steps of: (a) operating the entire CMOS microcomputer at the first frequency while accessing the first memory, causing the CMOS microcomputer to dissipate power at a first level; (b) determining from a user program currently being executed that it is necessary to access the second memory; and (c) in response to the determining of step (b), operating the entire CMOS microcomputer at the second frequency while accessing the second memory, causing the CMOS microcomputer to dissipate power at a second level which is lower than the first level.
Claim 3
Dependent Claim
57 words
The method of claim 1 wherein the first memory is internal to the CMOS microcomputer and the second memory is external to the CMOS microcomputer, and wherein step (b) includes executing the program to set a first speed control bit to a first level indicating that the second memory is to be accessed at the second frequency.
Claim 4
Dependent Claim
32 words
The method of claim 2 including selecting the second frequency as a system clock frequency for the entire CMOS microcomputer in response to the first level of the first speed control bit.
Claim 5
Dependent Claim
35 words
The method of claim 3 including dividing a fast clock having the first frequency by a predetermined factor in response to the first level of the first speed control bit to derive the second frequency.
Claim 6
Dependent Claim
53 words
The method of claim 4 wherein the CMOS microcomputer includes a plurality of chip control outputs, the method including selecting the second frequency as the system clock frequency in response to a coincidence of one of a plurality of speed control bits and a corresponding one of the plurality of chip control outputs.
Claim 7
Dependent Claim
140 words
The method of claim 4 wherein the CMOS microcomputer includes a speed control register and a chip select output decoder that decodes memory addresses to produce a plurality of chip select output signals, the method including operating the program to enter information into bits of the speed control register to determine whether a fast clock source or a slow clock source is to be selected to determine the frequency at which the entire CMOS microcomputer operates, to determine whether a signal from the fast clock source is to be divided to derive a divided down frequency at which the entire CMOS microcomputer operates, and to determine which of the plurality of chip select output signals must be produced in coincidence with information in the speed control register to cause the entire CMOS microcomputer to operate at the divided down frequency.
Claim 8
Independent Claim
300 words
A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a first frequency, a second memory operable at a second frequency, the first frequency being higher than the second frequency, the method comprising the steps of: (a) operating the entire CMOS microcomputer at the first frequency while accessing the first memory, causing the CMOS microcomputer to dissipate power at a first level; (b) determining from a user program currently being executed that it is necessary to access the second memory; and (c) in response to the determining of step (b), operating the entire CMOS microcomputer at the second frequency while accessing the second memory, causing the CMOS microcomputer to dissipate power at a second level which is lower than the first level, wherein the CMOS microcomputer includes a programmable speed control register and a chip select output decoder that decodes memory addresses to produce a plurality of chip select output signals, and also includes a programmable chip select register adapted to enable the various chip select outputs, the method including operating the program to enter information into bits of the speed control register to determine whether a fast clock source or a slow clock source is to be selected to determine the frequency at which the entire CMOS microcomputer operates, to determine whether a signal from the fast clock source is to be divided to derive a divided down frequency at which the entire CMOS microcomputer operates, and operating the program to enter information into bits of the chip select register to determine which of the plurality of chip select output signals must be produced in coincidence with information in the speed control register to cause the entire CMOS microcomputer to operate at the divided down frequency.
Claim 9
Independent Claim
300 words
A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a first frequency, a second memory operable at a second frequency, the first frequency being higher than the second frequency, the method comprising the steps of: (a) operating the entire CMOS microcomputer at the first frequency while accessing the first memory, causing the CMOS microcomputer to dissipate power at a first level; (b) determining from a user program currently being executed that it is necessary to access the second memory; and (c) in response to the determining of step (b), operating the entire CMOS microcomputer at the second frequency while accessing the second memory, causing the CMOS microcomputer to dissipate power at a second level which is lower than the first level, wherein the CMOS microcomputer includes a programmable speed control register and a chip select output decoder that decodes memory addresses to produce a plurality of chip select output signals, and also includes a programmable chip select register adapted to enable the various chip select outputs, the method including operating the program to enter information into bits of the speed control register to determine whether a fast clock source or a slow clock source is to be selected to determine the frequency at which the entire CMOS microcomputer operates, to determine whether a signal from the fast clock source is to be divided to derive a divided down frequency at which the entire CMOS microcomputer operates, and operating the program to enter information into bits of the chip select register to determine which of the plurality of chip select output signals must be produced in coincidence with information in the speed control register to cause the entire CMOS microcomputer to operate at the divided down frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |