Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
121 words
An apparatus comprising: a received waveform containing an information signal encoded at periodic time instants of a known period for eliminating an undesired amplitude error in said received waveform where said undesired amplitude error is slowly varying with respect to said known period and recovering a desired periodic time instants: a delay element for delaying said received waveform, to provide a delayed waveform, by an amount equal to said known period; a subtracting element for comparing said received waveform with said delayed waveform, and providing a timing recovery signal with zero crossing substantially less corrupted by said undesired amplitude error; and averaging circuitry, said averaging circuitry operating on said timing recovery signal for purposes of recovering said desired periodic time instants.
Claim 2
Independent Claim
121 words
An apparatus comprising: a received waveform containing an information signal encoded at periodic time instants of a known period for eliminating an undesired amplitude error in said received waveform where said undesired amplitude error is slowly varying with respect to said known period and recovering a desired periodic time instants: a delay element for delaying said received waveform, to provide a delayed waveform, by an amount equal to said known period; a subtracting element for comparing said received waveform with said delayed waveform, and providing a timing recovery signal with zero crossing substantially less corrupted by said undesired amplitude error; and averaging circuitry, said averaging circuitry operating on said timing recovery signal for purposes of recovering said desired periodic time instants.
Claim 3
Dependent Claim
19 words
The apparatus of claim 1, wherein the information signal is comprised of data levels varying about a center reference.
Claim 4
Dependent Claim
29 words
The apparatus of claim 1, wherein the information signal is comprised of binary data levels equally offset about a center reference, with a bitsync preamble consisting of alternating values.
Claim 5
Dependent Claim
31 words
The apparatus of claim 1, wherein said delay element further comprises: a sampling element; an analog to digital converter; a memory writing processor; a memory reading processor; and a delay clock.
Claim 6
Dependent Claim
15 words
The apparatus of claim 1, wherein the subtracting element includes a computing arithmetic logic circuitry.
Claim 7
Dependent Claim
27 words
The apparatus of claim 1, wherein the averaging circuitry comprises a phase locked loop, said phase locked loop providing filtering and jitter removal on said zero crossings.
Claim 8
Dependent Claim
34 words
The apparatus of claim 1, wherein the averaging circuitry establishes the timing recovery signal based on alternating preamble, and then excludes zero crossings that occur outside a predetermined threshold of the zero crossing instants.
Claim 9
Dependent Claim
14 words
The apparatus of claim 1, wherein the known period is a predetermined selectable threshold.
Claim 10
Independent Claim
128 words
An apparatus comprising: an information signal encoded at periodic time instants of a known period in a received waveform, for eliminating an undesired amplitude error in said received waveform where said undesired amplitude error is slowly varying with respect to said known period and recovering a desired periodic time instants: a microprocessor having: a delay element for delaying said received waveform, to provide a delayed waveform, by an amount equal to said known period: and a subtracting element for comparing said received waveform with said delayed waveform, and providing a timing recovery signal with zero crossing substantially less corrupted by said undesired amplitude error; and averaging circuitry, said averaging circuitry operating to reduce jitter in said timing recovery signal for purposes of recovering said desired periodic time instants.
Claim 11
Independent Claim
128 words
An apparatus comprising: an information signal encoded at periodic time instants of a known period in a received waveform, for eliminating an undesired amplitude error in said received waveform where said undesired amplitude error is slowly varying with respect to said known period and recovering a desired periodic time instants: a microprocessor having: a delay element for delaying said received waveform, to provide a delayed waveform, by an amount equal to said known period: and a subtracting element for comparing said received waveform with said delayed waveform, and providing a timing recovery signal with zero crossing substantially less corrupted by said undesired amplitude error; and averaging circuitry, said averaging circuitry operating to reduce jitter in said timing recovery signal for purposes of recovering said desired periodic time instants.