Method and apparatus for data path circuit layout design and memory medium for causing computer to execute data path circuit layout design

Claim 2

A data path circuit layout design method of generating a mask layout of a data path circuit comprising a plurality of function blocks, said data path circuit layout design method characterized in that there are prepared (i) function macros in each of which there is defined an expansion, according to the parameters, to a circuit comprising a plurality of schematic leaf cells and (ii) layout leaf cells corresponding to said schematic leaf cells, and said data path circuit layout design method comprising: a function macro placement process for determining, for a data path circuit of which function blocks are described by function macros, the placement of said function blocks so as to optimize the value of a predetermined objective function; a function macro expansion process for expanding each of said function macros describing said function blocks, to a circuit comprising a plurality of schematic leaf cells and for preparing connection information on the schematic leaf cell level; and a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells and for wiring said layout leaf cells to one another, said replacing and said wiring being made based on said placement of said function blocks determined by said function macro placement process and on said connection information on the schematic leaf cell level prepared by said function macro expansion process.

Claim 3

A data path circuit layout design method according to claim 1, wherein signal delay constraints are given to each signal line between function blocks, and said objective function in said function macro placement process has a term representing information of deviation from said signal delay constraints.

Claim 4

A data path circuit layout design method according to claim 2, wherein each of said function macros has a parameter which specifies the circuit output drive ability, and said method further comprising, after said function macro placement process, a drive ability optimization process arranged such that the signal delay time of each signal line between function blocks is obtained, and that when there is a signal line which does not satisfy the signal delay constraints, there is changed the output drive ability specifying parameter of the function macro which describes the function block at the output side of said signal line, such that said signal delay constraints are satisfied.

Claim 5

A data path circuit layout design method according to claim 2, wherein said function macro expansion process has a process for changing the output drive ability of the schematic leaf cell for driving a plurality of schematic leaf cells in each of said function blocks such that said signal delay constraints are satisfied.

Claim 6

A data path circuit layout design method according to claim 1, wherein: data path circuit contour conditions are given; and said objective function in said function macro placement process has a term representing the degree of satisfaction with respect to said contour conditions.

Claim 7

A data path circuit layout design method according to claim 5, wherein: a plurality of layout leaf cells respectively having different outer shapes are prepared for each of said schematic leaf cells; said function macro expansion process has a process for selecting a layout leaf cell for each of said schematic leaf cells such that said contour conditions are satisfied; and said detail placement and routing process has a process for replacing said schematic leaf cells with said layout leaf cells selected in said function macro expansion process.

Claim 8

A data path circuit layout design method according to claim 5, further comprising, after said function macro expansion process, a cell placement improvement process for exchanging the placement of said schematic leaf cells such that the value of said predetermined objective function is optimized.

Claim 9

A data path circuit layout design method according to claim 5, wherein said function macro placement process has a process for placing a plurality of function blocks in line in the data signal transmitting direction and for placing a plurality of adjacent function blocks in each column in the direction at a right angle to said data signal transmitting direction.

Claim 10

A data path circuit layout design method according to claim 5, further comprising, after said function macro expansion process, a cell regeneration process for generating layout leaf cells having such shapes as to satisfy said contour conditions, based on said connection information on the schematic leaf cell level prepared in said function macro expansion process.

Claim 11

A data path circuit layout design method according to claim 1, wherein said objective function in said function macro placement process has a term representing the number of wiring lines, out of the wiring lines passing through each of said function blocks, which cannot pass through the routing track, a term representing the total wiring length of the signal lines connecting said function blocks to one another, and a term representing information of deviation from delay constraints of each of said signal lines.

Claim 12

A data path circuit layout design method of generating a mask layout of a data path circuit of which specifications are described in a function description language, said data path circuit layout design method characterized in that there are prepared a plurality of schematic leaf cells and layout leaf cells corresponding to said schematic leaf cells, said data path circuit layout design method comprising: a logic synthesis process for generating a circuit comprising schematic leaf cells by logic synthesis and for preparing connection information on the schematic leaf cell level, said generation and preparation being made based on said specifications described in said function description language; a regularity extraction process for collecting, in said circuit comprising schematic leaf cells generated by said logic synthesis process, a plurality of schematic leaf cells having a common nature, into one function block such that there is generated a circuit comprising a plurality of such function blocks; a function block placement process for determining, in said circuit comprising a plurality of function blocks generated by said regularity extraction process, the placement of said function blocks such that the value of a predetermined objective function is optimized; and a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said connection information on the schematic leaf cell level prepared by said logic synthesis process and on said function block placement determined by said function block placement process.

Claim 13

A data path circuit layout design method of generating a mask layout of a data path circuit of which specifications are described in a function description language, said data path circuit layout design method characterized in that there are prepared a plurality of schematic leaf cells and layout leaf cells corresponding to said schematic leaf cells, said data path circuit layout design method comprising: a logic synthesis process for generating a circuit comprising schematic leaf cells by logic synthesis and for preparing connection information on the schematic leaf cell level, said generation and preparation being made based on said specifications described in said function description language; a regularity extraction process for collecting, in said circuit comprising schematic leaf cells generated by said logic synthesis process, a plurality of schematic leaf cells having a common nature, into one function block such that there is generated a circuit comprising a plurality of such function blocks; a function block placement process for determining, in said circuit comprising a plurality of function blocks generated by said regularity extraction process, the placement of said function blocks such that the value of a predetermined objective function is optimized; and a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said connection information on the schematic leaf cell level prepared by said logic synthesis process and on said function block placement determined by said function block placement process.

Claim 14

A data path circuit layout design method according to claim 11, wherein signal delay constraints are given, and said objective function in said function block placement process has a term representing information of deviation from said signal delay constraints.

Claim 15

A data path circuit layout design method according to claim 12, further comprising, after said function block placement process, a drive ability optimization process arranged such that the signal delay time of each signal line between function blocks is obtained, and that when there is a signal line which does not satisfy said signal delay constraints, there is changed the output drive ability of the schematic leaf cells in the function block at the output side of said signal line such that said signal delay constraints are satisfied.

Claim 16

A data path circuit layout design method according to claim 12, further comprising, after said function block placement process, a drive ability optimization process for changing the schematic leaf cell output drive ability for driving a plurality of schematic leaf cells in each of said function blocks such that said signal delay constraints are satisfied.

Claim 17

A data path circuit layout design method according to claim 11, wherein: data path circuit contour conditions are given; and said objective function in said function block placement process has a term representing the degree of satisfaction with respect to said contour conditions.

Claim 18

A data path circuit layout design method according to claim 15, further comprising, before said detail placement and routing process, a cell placement improvement process for exchanging the placement of said schematic leaf cells such that the value of said predetermined objective function is optimized.

Claim 19

A data path circuit layout design method according to claim 15, wherein said function block placement process has a process for placing a plurality of function blocks in line in the data signal transmitting direction and for placing a plurality of adjacent function blocks in each column in the direction at a right angle to said data signal transmitting direction.

Claim 20

A data path circuit layout design apparatus for generating a mask layout of a data path circuit comprising a plurality of function blocks, comprising: memory means which stores pieces of information relating to (i) function macros in each of which there is defined an expansion, according to the parameters, to a circuit comprising a plurality of schematic leaf cells and (ii) layout leaf cells corresponding to said schematic leaf cells; input means for entering the design information of a data path circuit of which function blocks are described by function macros; a central process unit for executing (i) a function macro placement process for determining, based on said data path circuit design information entered by said input means, the placement of said function blocks such that the value of a predetermined objective function is optimized, (ii) a function macro expansion process for expanding, with the use of information stored in said memory means, each of said function macros describing said function blocks to a circuit comprising a plurality of schematic leaf cells, and for preparing connection information on the schematic leaf cell level, and (iii) a detail placement and routing process for generating a mask layout by replacing, with the use of information stored in said memory means, said schematic leaf cells with the corresponding layout leaf cells and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said function block placement determined by said function macro placement process and on said connection information on the schematic leaf cell level prepared by said function macro expansion process; and output means for supplying said mask layout generated by said detail placement and routing process.

Claim 21

A data path circuit layout design apparatus for generating a mask layout of a data path circuit comprising a plurality of function blocks, comprising: memory means which stores pieces of information relating to (i) function macros in each of which there is defined an expansion, according to the parameters, to a circuit comprising a plurality of schematic leaf cells and (ii) layout leaf cells corresponding to said schematic leaf cells; input means for entering the design information of a data path circuit of which function blocks are described by function macros; a central process unit for executing (i) a function macro placement process for determining, based on said data path circuit design information entered by said input means, the placement of said function blocks such that the value of a predetermined objective function is optimized, (ii) a function macro expansion process for expanding, with the use of information stored in said memory means, each of said function macros describing said function blocks to a circuit comprising a plurality of schematic leaf cells, and for preparing connection information on the schematic leaf cell level, and (iii) a detail placement and routing process for generating a mask layout by replacing, with the use of information stored in said memory means, said schematic leaf cells with the corresponding layout leaf cells and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said function block placement determined by said function macro placement process and on said connection information on the schematic leaf cell level prepared by said function macro expansion process; and output means for supplying said mask layout generated by said detail placement and routing process.

Claim 22

A data path circuit layout design apparatus for generating a mask layout of a data path circuit of which specifications are described in a function description language, comprising: memory means which stores pieces of information relating to (i) a plurality of schematic leaf cells and (ii) layout leaf cells corresponding to said schematic leaf cells; input means for entering data path circuit specification described in a description language; a central process unit for executing (i) a logic synthesis process for generating a circuit comprising schematic leaf cells by logic synthesis and for preparing connection information on the schematic leaf cell level, said generation and said preparation being made with the use of information stored in said memory means based on said data path circuit specifications entered by said input means, (ii) a regularity extraction process for collecting, in said circuit comprising schematic leaf cells generated by said logic synthesis process, a plurality of schematic leaf cells having a common nature, into one function block such that there is generated a circuit comprising a plurality of such function blocks, (iii) a function block placement process for determining, in said circuit comprising a plurality of function blocks generated by said regularity extraction process, the placement of said function blocks such that the value of a predetermined objective function is optimized; and (iv) a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells with the use of information stored in said memory means and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said connection information on the schematic leaf cell level prepared by said logic synthesis process and on said function block placement determined by said function block placement process; and output means for supplying said mask layout generated by said detail placement and routing process.

Claim 23

A data path circuit layout design apparatus for generating a mask layout of a data path circuit of which specifications are described in a function description language, comprising: memory means which stores pieces of information relating to (i) a plurality of schematic leaf cells and (ii) layout leaf cells corresponding to said schematic leaf cells; input means for entering data path circuit specification described in a description language; a central process unit for executing (i) a logic synthesis process for generating a circuit comprising schematic leaf cells by logic synthesis and for preparing connection information on the schematic leaf cell level, said generation and said preparation being made with the use of information stored in said memory means based on said data path circuit specifications entered by said input means, (ii) a regularity extraction process for collecting, in said circuit comprising schematic leaf cells generated by said logic synthesis process, a plurality of schematic leaf cells having a common nature, into one function block such that there is generated a circuit comprising a plurality of such function blocks, (iii) a function block placement process for determining, in said circuit comprising a plurality of function blocks generated by said regularity extraction process, the placement of said function blocks such that the value of a predetermined objective function is optimized; and (iv) a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells with the use of information stored in said memory means and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said connection information on the schematic leaf cell level prepared by said logic synthesis process and on said function block placement determined by said function block placement process; and output means for supplying said mask layout generated by said detail placement and routing process.

Claim 24

A memory medium for causing a computer to execute a data path circuit layout design for generating a mask layout of a data path circuit comprising a plurality of function blocks, said memory medium storing: (i) function macros in each of which there is defined an expansion, according to the parameters, to a circuit comprising a plurality of schematic leaf cells and (ii) layout leaf cells corresponding to said schematic leaf cells; and a program for causing a computer to execute, a function macro placement process for determining, for a data path circuit of which function blocks are described by function macros, the placement of said function blocks so as to optimize the value of a predetermined objective function, a function macro expansion process for expanding each of said function macros describing said function blocks, to a circuit comprising a plurality of schematic leaf cells and for preparing connection information on the schematic leaf cell level, and a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said function block placement determined by said function macro placement process and on said connection information on the schematic leaf cell level prepared by said function macro expansion process.

Claim 25

A memory medium for causing a computer to execute a data path circuit layout design for generating a mask layout of a data path circuit comprising a plurality of function blocks, said memory medium storing: (i) function macros in each of which there is defined an expansion, according to the parameters, to a circuit comprising a plurality of schematic leaf cells and (ii) layout leaf cells corresponding to said schematic leaf cells; and a program for causing a computer to execute, a function macro placement process for determining, for a data path circuit of which function blocks are described by function macros, the placement of said function blocks so as to optimize the value of a predetermined objective function, a function macro expansion process for expanding each of said function macros describing said function blocks, to a circuit comprising a plurality of schematic leaf cells and for preparing connection information on the schematic leaf cell level, and a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said function block placement determined by said function macro placement process and on said connection information on the schematic leaf cell level prepared by said function macro expansion process.

Claim 26

A memory medium for causing a computer to execute a data path circuit layout design for generating a mask layout of a data path circuit of which specifications are described in a function description language, said memory medium storing: a plurality of schematic leaf cells and layout leaf cells corresponding to said schematic leaf cells; and a program for causing a computer to execute, a logic synthesis process for generating a circuit comprising schematic leaf cells by logic synthesis and for preparing connection information on the schematic leaf cell level, said generation and said preparation being made based on specifications described in a function description language, a regularity extraction process for collecting, in said circuit comprising schematic leaf cells generated by said logic synthesis process, a plurality of schematic leaf cells having a common nature, into one function block such that there is generated a circuit comprising a plurality of such function blocks, a function block placement process for determining, in said circuit comprising a plurality of function blocks generated by said regularity extraction process, the placement of said function blocks such that the value of a predetermined objective function is optimized, and a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said connection information on the schematic leaf cell level prepared by said logic synthesis process and on said function block placement determined by said function block placement process.

Claim 27

A memory medium for causing a computer to execute a data path circuit layout design for generating a mask layout of a data path circuit of which specifications are described in a function description language, said memory medium storing: a plurality of schematic leaf cells and layout leaf cells corresponding to said schematic leaf cells; and a program for causing a computer to execute, a logic synthesis process for generating a circuit comprising schematic leaf cells by logic synthesis and for preparing connection information on the schematic leaf cell level, said generation and said preparation being made based on specifications described in a function description language, a regularity extraction process for collecting, in said circuit comprising schematic leaf cells generated by said logic synthesis process, a plurality of schematic leaf cells having a common nature, into one function block such that there is generated a circuit comprising a plurality of such function blocks, a function block placement process for determining, in said circuit comprising a plurality of function blocks generated by said regularity extraction process, the placement of said function blocks such that the value of a predetermined objective function is optimized, and a detail placement and routing process for generating a mask layout by replacing said schematic leaf cells with the corresponding layout leaf cells and by wiring said layout leaf cells to one another, said replacing and said wiring being made based on said connection information on the schematic leaf cell level prepared by said logic synthesis process and on said function block placement determined by said function block placement process.