US5737192A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Density improvement in integration modules
Assignee: United States Department of the Air Force
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Filing: 1995-07-10
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Granted: 1998-04-07
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Expires: 2015-07-10
Abstract
Abstract Chip-like stacks of thinned chips are mounted in wells etched into a substrate. A"chip-like" stack is a stack of chips, which in the aggregate have a height approximately equal to that of a single conventional chip. These chip-like stacks are mounted in a variety of packages. In a preferred embodiment, the stacks are mounted in wells within the substrate of an integrated circuit and the stack is provided with a patterned overlay so that all the circuit connections can be made from the upper surface of the stack. The patterned overlay is protected by a planar insulator. A plurality of substrates may be stacked, one upon the other.
Inventors
- 👤 Richard W. Linderman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:35
CPC Classifications
H; H10; H10W; H10W90/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
78 words
A chip-like stack of wafers comprising: at least one of said wafers having side and top surfaces; said at least one wafer having further a beveled edge extending between said side and top surfaces; conductive means connected to said at least one wafer; said conductive means extending along the side surface over said beveled edge to the top surface; and said conductive means being further connected electrically to side surfaces of all other wafers in said chip-like stack.
Claim 2
Dependent Claim
78 words
A chip-like stack of wafers comprising: at least one of said wafers having side and top surfaces; said at least one wafer having further a beveled edge extending between said side and top surfaces; conductive means connected to said at least one wafer; said conductive means extending along the side surface over said beveled edge to the top surface; and said conductive means being further connected electrically to side surfaces of all other wafers in said chip-like stack.
Claim 3
Independent Claim
78 words
The method of using an integration module, comprising the steps of: (a) connecting to a first water positioned in a well in a substrate, said first wafer having a beveled edge extending between a side and a top surface, and said first wafer being a component of a stack of wafers positioned in said well, the members of said stack being connected to each other along their side surfaces; and (b) energizing a connection to said first wafer.
Claim 4
Independent Claim
78 words
The method of using an integration module, comprising the steps of: (a) connecting to a first water positioned in a well in a substrate, said first wafer having a beveled edge extending between a side and a top surface, and said first wafer being a component of a stack of wafers positioned in said well, the members of said stack being connected to each other along their side surfaces; and (b) energizing a connection to said first wafer.
Claim 5
Dependent Claim
17 words
The method as defined in claim 2, further including the step of energizing said stack of wafers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |