Patent US5736880A successfully refreshed from Google Patents.
US5736880A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential charge pump using surtchingly controlled current generators
Assignee: STMicroelectronics SRL
•
Filing: 1995-12-21
•
Granted: 1998-04-07
•
Expires: 2015-12-21
Abstract
Abstract A differential charge pump circuit employing a lowpass filter network which is chargeable and dischargeable by switchingly controlled current generators. The differential charge pump employs two identical current generators for injecting the same current I in a substantially continuous manner, on the two significant nodes of the lowpass filter. The differential charge pump also employs two pairs of identical, switchingly controlled current generators connected to the two significant nodes, respectively, each capable of pulling a current I. The two generators forming each of the two pairs of switchingly controlled current generators are controlled by one of a pair of control signals (UP, DOWN) and by the inverted signal of the other of the pair of control signals, respectively. All four switchingly controlled generators may be of the same type (N-type), thus ensuring high speed and precision. The two identical (P-type) current generators employed for continuously injecting the same current I on the two nodes of the lowpass filter may be controlled through a common mode feedback loop for enhanced precision.
Inventors
- 👤 Melchiorre Bruccoleri
- 👤 Gaetano Cosentino
- 👤 Marco Demicheli
- 👤 Giuseppe Patti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:28
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0896
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
338 words
A differential charge pump circuit comprising: a lowpass filter having a first node and a second node, the low pass filter including a resistor that is coupled in series with a first capacitor between the first and second nodes and a second capacitor that is coupled between the first and second nodes and is in parallel with the resistor and the first capacitor across the first and second nodes; a first current generator coupled to the first node to inject a substantially continuous first current into the first node; a second current generator coupled to the second node to inject a substantially continuous second current into the second node, the second current being equal to the first current; first means, responsive to a first CMOS logic level control signal and an inverse of the first logic level CMOS control signal, for pulling current from the first and second nodes of the lowpass filter, the first means including means for switching from pulling a current equal to the first current from the first node when the first CMOS logic level control signal is deasserted to pulling a current equal to the second current from the second node when the first CMOS logic level control signal is asserted; and second means, responsive to a second CMOS logic level control signal and an inverse of the second CMOS logic level control signal, for pulling current from the first and second nodes of the lowpass filter, the second means including means for switching from pulling a current equal to the first current from the first node when the second CMOS logic level control signal is asserted to pulling a current equal to the second current from the second node when the second CMOS logic level control signal is deasserted; wherein the means for switching included in the first means includes resistive means for insulating the first CMOS logic level control signal and the inverse of the first CMOS logic level control signal from a capacitance of the first means for pulling current.
Claim 2
Dependent Claim
338 words
A differential charge pump circuit comprising: a lowpass filter having a first node and a second node, the low pass filter including a resistor that is coupled in series with a first capacitor between the first and second nodes and a second capacitor that is coupled between the first and second nodes and is in parallel with the resistor and the first capacitor across the first and second nodes; a first current generator coupled to the first node to inject a substantially continuous first current into the first node; a second current generator coupled to the second node to inject a substantially continuous second current into the second node, the second current being equal to the first current; first means, responsive to a first CMOS logic level control signal and an inverse of the first logic level CMOS control signal, for pulling current from the first and second nodes of the lowpass filter, the first means including means for switching from pulling a current equal to the first current from the first node when the first CMOS logic level control signal is deasserted to pulling a current equal to the second current from the second node when the first CMOS logic level control signal is asserted; and second means, responsive to a second CMOS logic level control signal and an inverse of the second CMOS logic level control signal, for pulling current from the first and second nodes of the lowpass filter, the second means including means for switching from pulling a current equal to the first current from the first node when the second CMOS logic level control signal is asserted to pulling a current equal to the second current from the second node when the second CMOS logic level control signal is deasserted; wherein the means for switching included in the first means includes resistive means for insulating the first CMOS logic level control signal and the inverse of the first CMOS logic level control signal from a capacitance of the first means for pulling current.
Claim 3
Dependent Claim
373 words
A differential charge pump circuit comprising: a lowpass filter having a first node and a second node, the low pass filter including a resistor that is coupled in series with a first capacitor between the first and second nodes and a second capacitor that is coupled between the first and second nodes and is in parallel with the resistor and the first capacitor across the first and second nodes; a first current generator coupled to the first node to inject a substantially continuous first current into the first node; a second current generator coupled to the second node to inject a substantially continuous second current into the second node, the second current being equal to the first current; first means, responsive to a first CMOS logic level control signal and an inverse of the first logic level CMOS control signal, for pulling current from the first and second nodes of the lowpass filter, the first means including means for switching from pulling a current equal to the first current from the first node when the first CMOS logic level control signal is deasserted to pulling a current equal to the second current from the second node when the first CMOS logic level control signal is asserted; and second means, responsive to a second CMOS logic level control signal and an inverse of the second CMOS logic level control signal, for pulling current from the first and second nodes of the lowpass filter, the second means including means for switching from pulling a current equal to the first current from the first node when the second CMOS logic level control signal is asserted to pulling a current equal to the second current from the second node when the second CMOS logic level control signal is deasserted; wherein the first means includes a current source that generates a continuous current, and the switching means included in the first means includes first and second current mirroring means, the first current mirroring means mirroring the continuous current generated by the current source when the first CMOS logic level control signal is deasserted, and the second current mirroring means mirroring the continuous current generated by the current source when the first CMOS logic level control signal is asserted.
Claim 4
Dependent Claim
373 words
A differential charge pump circuit comprising: a lowpass filter having a first node and a second node, the low pass filter including a resistor that is coupled in series with a first capacitor between the first and second nodes and a second capacitor that is coupled between the first and second nodes and is in parallel with the resistor and the first capacitor across the first and second nodes; a first current generator coupled to the first node to inject a substantially continuous first current into the first node; a second current generator coupled to the second node to inject a substantially continuous second current into the second node, the second current being equal to the first current; first means, responsive to a first CMOS logic level control signal and an inverse of the first logic level CMOS control signal, for pulling current from the first and second nodes of the lowpass filter, the first means including means for switching from pulling a current equal to the first current from the first node when the first CMOS logic level control signal is deasserted to pulling a current equal to the second current from the second node when the first CMOS logic level control signal is asserted; and second means, responsive to a second CMOS logic level control signal and an inverse of the second CMOS logic level control signal, for pulling current from the first and second nodes of the lowpass filter, the second means including means for switching from pulling a current equal to the first current from the first node when the second CMOS logic level control signal is asserted to pulling a current equal to the second current from the second node when the second CMOS logic level control signal is deasserted; wherein the first means includes a current source that generates a continuous current, and the switching means included in the first means includes first and second current mirroring means, the first current mirroring means mirroring the continuous current generated by the current source when the first CMOS logic level control signal is deasserted, and the second current mirroring means mirroring the continuous current generated by the current source when the first CMOS logic level control signal is asserted.
Claim 5
Dependent Claim
34 words
The differential charge pump of claim 2, wherein the first and second current mirroring means each include means for reducing transients by decreasing transient duration within the first and second current mirroring means, respectively.
Claim 6
Dependent Claim
313 words
A differential charge pump circuit comprising: a lowpass filter having a first node and a second node, the low pass filter including a resistor that is coupled in series with a first capacitor between the first and second nodes, and a second capacitor that is coupled between the first and second nodes and is in parallel with the resistor and the first capacitor across the first and second nodes; a first current generator coupled to the first node to inject a substantially continuous first current into the first node; a second current generator coupled to the second node to inject a substantially continuous second current into the second node, the second current being equal to the first current; a first switchingly controlled current generator coupled to the first and second nodes, the first switchingly controlled current generator having a first current source that provides a continuous current and a pair of switchingly controlled current mirrors coupled to the first current source, a first switchingly controlled current mirror of the pair coupled to the first node and being responsive to an inverse of a first CMOS logic level control signal, and a second switchingly controlled current mirror of the pair coupled to the second node and being responsive to the first CMOS logic level control signal; and a second switchingly controlled current generator coupled to the first and second nodes, the second switchingly controlled current generator having a second current source that provides a continuous current and a pair of switchingly controlled current mirrors coupled to the second current source, a first switchingly controlled current mirror of the pair coupled to the first node and being responsive to a second CMOS logic level control signal, and a second switchingly controlled current mirror of the pair coupled to the second node and being responsive to an inverse of the second CMOS logic level control signal.
Claim 7
Dependent Claim
313 words
A differential charge pump circuit comprising: a lowpass filter having a first node and a second node, the low pass filter including a resistor that is coupled in series with a first capacitor between the first and second nodes, and a second capacitor that is coupled between the first and second nodes and is in parallel with the resistor and the first capacitor across the first and second nodes; a first current generator coupled to the first node to inject a substantially continuous first current into the first node; a second current generator coupled to the second node to inject a substantially continuous second current into the second node, the second current being equal to the first current; a first switchingly controlled current generator coupled to the first and second nodes, the first switchingly controlled current generator having a first current source that provides a continuous current and a pair of switchingly controlled current mirrors coupled to the first current source, a first switchingly controlled current mirror of the pair coupled to the first node and being responsive to an inverse of a first CMOS logic level control signal, and a second switchingly controlled current mirror of the pair coupled to the second node and being responsive to the first CMOS logic level control signal; and a second switchingly controlled current generator coupled to the first and second nodes, the second switchingly controlled current generator having a second current source that provides a continuous current and a pair of switchingly controlled current mirrors coupled to the second current source, a first switchingly controlled current mirror of the pair coupled to the first node and being responsive to a second CMOS logic level control signal, and a second switchingly controlled current mirror of the pair coupled to the second node and being responsive to an inverse of the second CMOS logic level control signal.
Claim 8
Dependent Claim
64 words
The differential charge pump of claim 4, wherein the first switchingly controlled current mirror includes: a first transistor having a first terminal coupled to the first current source and having a second terminal that is a control terminal to receive the inverse of the first CMOS logic level control signal; and a bipolar current mirror coupled to a third terminal of the first transistor.
Claim 9
Dependent Claim
39 words
The differential charge pump of claim 5, wherein the first transistor is an NMOS transistor and the switchingly controlled current mirror further includes a resistor coupled between the third terminal of the first transistor and the bipolar current mirror.
Claim 10
Dependent Claim
46 words
The differential charge pump of claim 4, further comprising: a common mode voltage feedback circuit coupled to the first and second nodes and the first and second current generators, the common mode voltage feedback circuit providing a regulation signal to the first and second current generators.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |