Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
164 words
A method of operating a processor having a plurality of modes of operation, comprising the steps of: providing at least two different operating systems for said processor; executing a task on said processor under one of said two different operating systems, including generating a task data structure for said task, said task executing in a given one mode of said plurality of modes of operation; creating a virtual vector table for each one of said plurality of modes of operation; generating an interrupt of said task on said processor; referencing an interrupt handler in response to said interrupt, said interrupt handler being in native code of said processor; said interrupt handler saving state of said processor at the time of said interrupt by referencing said task data structure; said task data structure providing access to said virtual vector table for said given one mode of operation; executing said interrupt under said one of said operating systems from a vector in said virtual vector table.
Claim 2
Independent Claim
164 words
A method of operating a processor having a plurality of modes of operation, comprising the steps of: providing at least two different operating systems for said processor; executing a task on said processor under one of said two different operating systems, including generating a task data structure for said task, said task executing in a given one mode of said plurality of modes of operation; creating a virtual vector table for each one of said plurality of modes of operation; generating an interrupt of said task on said processor; referencing an interrupt handler in response to said interrupt, said interrupt handler being in native code of said processor; said interrupt handler saving state of said processor at the time of said interrupt by referencing said task data structure; said task data structure providing access to said virtual vector table for said given one mode of operation; executing said interrupt under said one of said operating systems from a vector in said virtual vector table.
Claim 3
Dependent Claim
26 words
A method according to claim 1 wherein said step of providing access includes storing a reference in said task data structure to said virtual vector table.
Claim 4
Dependent Claim
30 words
A method according to claim 1 wherein said interrupt handler operates at the highest level of priority of said processor to thereby be executed first upon occurrence of said interrupt.
Claim 5
Dependent Claim
27 words
A method according to claim 1 wherein said plurality of modes of operation include a 32-bit mode, a 64-bit mode, a big-endian mode and a little-endian mode.
Claim 6
Dependent Claim
25 words
A method according to claim 1 wherein said step of referencing said task data structure includes using contents of a hardware register of said processor.
Claim 7
Dependent Claim
19 words
A method according to claim 2 wherein said task data structure contains a pointer to said virtual vector table.
Claim 8
Dependent Claim
22 words
A method according to claim 1 wherein said plurality of modes of operation include a plurality of different modes of handling data.
Claim 9
Dependent Claim
166 words
An interrupt handler for a processor having a plurality of modes of operation and at least two different operating systems, comprising: a task executing on said processor under one of said two different operating systems, the task including generating a task data structure for said task, said task executing in a given one mode of said plurality of modes of operation; a virtual vector table for each one of said plurality of modes of operation; an interrupt generator for generating an interrupt for interrupting execution of said task on said processor; an interrupt handler referenced in response to said interrupt, said interrupt handler being in native code of said processor; said interrupt handler saving state of said processor at the time of said interrupt by referencing said task data structure; said task data structure accessing said virtual vector table for said given mode of operation; said interrupt being executed under said one of said two different operating systems from a vector in said virtual vector table.
Claim 10
Dependent Claim
166 words
An interrupt handler for a processor having a plurality of modes of operation and at least two different operating systems, comprising: a task executing on said processor under one of said two different operating systems, the task including generating a task data structure for said task, said task executing in a given one mode of said plurality of modes of operation; a virtual vector table for each one of said plurality of modes of operation; an interrupt generator for generating an interrupt for interrupting execution of said task on said processor; an interrupt handler referenced in response to said interrupt, said interrupt handler being in native code of said processor; said interrupt handler saving state of said processor at the time of said interrupt by referencing said task data structure; said task data structure accessing said virtual vector table for said given mode of operation; said interrupt being executed under said one of said two different operating systems from a vector in said virtual vector table.
Claim 11
Dependent Claim
23 words
Apparatus according to claim 8 wherein said reference to said task data structure includes using contents of a hardware register of said processor.
Claim 12
Dependent Claim
28 words
Apparatus according to claim 8 wherein said accessing of said virtual vector table includes using a stored reference in said task data structure to said virtual vector table.
Claim 13
Dependent Claim
18 words
Apparatus according to claim 10 wherein said task data structure contains a pointer to said virtual vector table.
Claim 14
Dependent Claim
29 words
Apparatus according to claim 8 wherein said interrupt handler operates at the highest level of priority of said processor to thereby be executed first upon occurrence of said interrupt.
Claim 15
Dependent Claim
21 words
Apparatus according to claim 8 wherein said plurality of modes of operation include a plurality of different modes of handling data.
Claim 16
Dependent Claim
27 words
Apparatus according to claim 13 wherein said plurality of modes of handling data include a 32-bit mode, a 64-bit mode, a big-endian mode and a little-endian mode.