Selective power supply control for battery saving effectively

Claim 2

A selective power supply control, which controls a power supply to a circuit for receiving an input signal, for battery saving, comprising: a bit rate detector for detecting a bit rate of the input signal; a bit pattern detector for detecting a predetermined bit pattern different from a preamble of the input signal; and a controller for controlling the power supply to said circuit in response to the result of the detection of the bit rate and the result of the detection of the bit pattern, wherein said controller supplies the power to said circuit continuously when both of a predetermined bit rate and a predetermined bit pattern are detected and supplies the power to said circuit at an interval when one of said predetermined bit rate and said predetermined bit pattern is not detected.

Claim 3

The control as claimed in claim 1, wherein said bit rate detector comprises: a detector for detecting a period of a transition of one of first logical level and second logical level of the input signal; and a decision circuit for deciding whether or not the period of the transition is within a predetermined range.

Claim 4

The control as claimed in claim 2, wherein said bit rate detector comprises: a leading edge detector for detecting said transition from the first logical level to the second logical level; and an interval counter for counting the period of said transition.

Claim 5

The control as claimed in claim 2, said bit rate detector further comprising: a counter for incrementing a count value when the period is within said predetermined range and for resetting the count value when the period is not within the predetermined range; and a comparator for comparing the count value with a predetermined reference value.

Claim 6

The control as claimed in claim 2, said predetermined value is an integral multiple of a unit bit length.

Claim 7

The control as claimed in claim 1, wherein said bit pattern detector comprises: a sampling circuit for sampling said input signal at a recovered clock from said input signal; and means for detecting whether or not said predetermined bit pattern exists in an output signal of said sampling circuit.

Claim 8

The control as claimed in claim 1, wherein said circuit is a radio section.

Claim 9

A selective power supply control which controls a power supply to a circuit for receiving an input signal, comprising: bit rate detecting means for detecting a bit rate of the input signal based on a transition of one of first and second logical levels of said input signal; bit pattern detecting means for detecting a predetermined bit pattern different from a preamble of said input signal; and control means for controlling a power supply to said circuit in response to both of the result of the bit rate detection and the result of the bit pattern detection, wherein said control means supplies the power to said circuit continuously when both of a predetermined bit rate and a predetermined bit pattern are detected and supplies the power to said circuit at an interval when one of said predetermined bit rate and said predetermined bit pattern is not detected.

Claim 10

A selective power supply control which controls a power supply to a circuit for receiving an input signal, comprising: bit rate detecting means for detecting a bit rate of the input signal based on a transition of one of first and second logical levels of said input signal; bit pattern detecting means for detecting a predetermined bit pattern different from a preamble of said input signal; and control means for controlling a power supply to said circuit in response to both of the result of the bit rate detection and the result of the bit pattern detection, wherein said control means supplies the power to said circuit continuously when both of a predetermined bit rate and a predetermined bit pattern are detected and supplies the power to said circuit at an interval when one of said predetermined bit rate and said predetermined bit pattern is not detected.

Claim 11

The control as claimed in claim 8, wherein said bit rate detecting means comprises: leading edge detecting means for detecting the transition from said first logical level to said second logical level of said input signal; interval counting means for counting a period of said transition; deciding means for deciding whether or not said period is within a predetermined range and for supplying a first signal when said period is within said predetermined range and a second signal when said period is not within said predetermined range.

Claim 12

The control as claimed in claim 9, said bit rate detecting means further comprising: counting means for incrementing a count value in response to said first signal and for resetting the count value in response to said second signal; and comparing means for comparing said count value with a predetermined reference value and for supplying a bit rate detecting signal when said count value is equal to the predetermined reference value.

Claim 13

The control as claimed in claim 9, said predetermined range is an integral multiple of a unit bit length.

Claim 14

A radio receiver comprising: a radio section for demodulating a received signal and for supplying a demodulated signal; a bit rate detector for detecting a transition of said demodulated signal from a first logical level to a second logical level, for counting a period of said transition, for deciding whether or not said period is within a predetermined range and for supplying a bit rate detection signal when said period is within said predetermined range; a bit pattern detector for detecting a predetermined bit pattern different from a preamble of said demodulated signal and for supplying a bit pattern detection signal when said bit pattern is detected; and a controller for controlling a power supply to said radio section in response to said bit rate detection signal and said bit pattern detection signal, wherein said controller supplies the power to said radio section continually when both a predetermined bit rate and a predetermined bit pattern are detected and supplies the power to said radio section at an interval when said predetermined bit rate is detected and said predetermined bit pattern is not detected.

Claim 15

A radio receiver comprising: a radio section for demodulating a received signal and for supplying a demodulated signal; a bit rate detector for detecting a transition of said demodulated signal from a first logical level to a second logical level, for counting a period of said transition, for deciding whether or not said period is within a predetermined range and for supplying a bit rate detection signal when said period is within said predetermined range; a bit pattern detector for detecting a predetermined bit pattern different from a preamble of said demodulated signal and for supplying a bit pattern detection signal when said bit pattern is detected; and a controller for controlling a power supply to said radio section in response to said bit rate detection signal and said bit pattern detection signal, wherein said controller supplies the power to said radio section continually when both a predetermined bit rate and a predetermined bit pattern are detected and supplies the power to said radio section at an interval when said predetermined bit rate is detected and said predetermined bit pattern is not detected.

Claim 18

The method for controlling the power supply as claimed in claim 13, wherein said step (a) comprises the step of: (d) detecting a period of the transition of one of a leading and trailing edges; (e) deciding whether or not the period is within a predetermined range; and (f) supplying the result of the decision.

Claim 19

The method for controlling the power supply as claimed in claim 13, wherein said step (b) comprises the step of: (g) sampling the input signal at a recovered clock from the input signal; and (h) detecting a predetermined pattern from the sampled signal.