US5734280A
Expired / Lapsed
US
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Semiconductor integrated circuit device having power on reset circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1996-07-15
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Granted: 1998-03-31
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Expires: 2016-07-15
Abstract
Abstract A semiconductor integrated circuit device has an internal circuit node reset signal generation circuit for inverting an output signal with a predetermined time lag immediately after application of power. The internal circuit node reset generation circuit comprises an initial stage power on reset signal generation circuit, an initial stage signal transmission circuit for inputting a signal outputted by the initial stage power on reset signal generation circuit, a final stage power on reset signal generation circuit for inputting a signal outputted by the initial stage signal transmission circuit, and a final stage signal transmission circuit for inputting a signal outputted by the power on reset signal and outputting the output signal. When an operating source voltage lower limit value of the initial stage power on reset signal generation circuit is lower than that of the final stage signal transmission circuit and a source voltage has not reached a predetermined value, it is possible for the final stage power on reset signal generation circuit to generate an output signal without being influenced by the initial stage power on reset signal generation circuit, and to output an internal circuit inactivation signal for a certain time after application of power, and an inversion signal after passing the certain time. As a result, a certain internal circuit initialization time may be exactly established.
Inventors
- 👤 Hirotoshi Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:14
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
137 words
A semiconductor integrated circuit device having an internal circuit node reset signal generation circuit for inverting an output signal with a predetermined time lag immediately after application of power, said internal circuit node reset generation circuit comprising: an initial stage power on reset signal generation circuit; an initial stage signal transmission circuit for inputting a signal outputted by said initial stage power on reset signal generation circuit; a final stage power on reset signal generation circuit for inputting a signal outputted by said initial stage signal transmission circuit; and a final stage signal transmission circuit for inputting a signal outputted by said power on reset signal and outputting the output signal; wherein an operating source voltage lower limit value of said initial stage signal transmission circuit is higher than that of said final stage signal transmission circuit.
Claim 2
Dependent Claim
137 words
A semiconductor integrated circuit device having an internal circuit node reset signal generation circuit for inverting an output signal with a predetermined time lag immediately after application of power, said internal circuit node reset generation circuit comprising: an initial stage power on reset signal generation circuit; an initial stage signal transmission circuit for inputting a signal outputted by said initial stage power on reset signal generation circuit; a final stage power on reset signal generation circuit for inputting a signal outputted by said initial stage signal transmission circuit; and a final stage signal transmission circuit for inputting a signal outputted by said power on reset signal and outputting the output signal; wherein an operating source voltage lower limit value of said initial stage signal transmission circuit is higher than that of said final stage signal transmission circuit.
Claim 3
Dependent Claim
45 words
The semiconductor integrated circuit device as set forth in claim 1, wherein said final stage power on reset signal generation circuit keeps an initial voltage value and immediately after application of power, said initial voltage value is transmitted to said final stage signal transmission circuit.
Claim 4
Dependent Claim
109 words
The semiconductor integrated circuit device as set forth in claim 1, wherein a) when a source voltage value has not reached a predetermined value immediately after application of power, i) said final stage signal transmission circuit operates, ii) said initial stage signal transmission circuit does not operate, and iii) said final stage power on reset signal generation circuit operates without being influenced by said initial stage power on reset signal generation circuit, and b) when the source voltage value has exceeded the predetermined value, the output signal of said initial stage power on reset signal generation circuit is transmitted to said final stage power on reset signal generation circuit.
Claim 5
Dependent Claim
43 words
The semiconductor integrated circuit device as set forth in claim 1, wherein said initial stage power reset on signal generation circuit includes an inversion potential deciding part comprising on of a PMOS transistor, a NMOS transistor, a bipolar transistor and a resistor element.
Claim 6
Dependent Claim
157 words
A semiconductor integrated circuit device comprising: an internal circuit node reset signal generation circuit including an initial stage power on reset signal generation circuit for inverting an output signal with a predetermined time lag immediately after application of power, an initial stage signal transmission circuit for inputting a signal outputted by said initial stage power on reset signal generation circuit, a final stage power on reset signal generation circuit for inputting a signal outputted by said initial stage signal transmission circuit, and a final stage signal transmission circuit for inputting a signal outputted by said final stage power on reset signal generation circuit and outputting an output signal; and a feedback circuit for inputting a signal corresponding to said output signal and a signal complementary to said output signal from said final stage signal transmission circuit, and outputting a signal which is an exclusive OR function of the input signals to said initial stage signal transmission circuit.
Claim 7
Dependent Claim
157 words
A semiconductor integrated circuit device comprising: an internal circuit node reset signal generation circuit including an initial stage power on reset signal generation circuit for inverting an output signal with a predetermined time lag immediately after application of power, an initial stage signal transmission circuit for inputting a signal outputted by said initial stage power on reset signal generation circuit, a final stage power on reset signal generation circuit for inputting a signal outputted by said initial stage signal transmission circuit, and a final stage signal transmission circuit for inputting a signal outputted by said final stage power on reset signal generation circuit and outputting an output signal; and a feedback circuit for inputting a signal corresponding to said output signal and a signal complementary to said output signal from said final stage signal transmission circuit, and outputting a signal which is an exclusive OR function of the input signals to said initial stage signal transmission circuit.
Claim 8
Dependent Claim
30 words
The semiconductor integrated circuit device as set forth in claim 5, further comprising a delay circuit connected between said feedback circuit and said internal circuit node reset signal generation circuit.
Claim 9
Dependent Claim
104 words
A semiconductor integrated circuit device having an internal circuit node reset signal generation circuit comprising: a power on reset signal generation circuit; a signal transmission circuit; and a normal operation detecting circuit, wherein said power on reset signal generation circuit generates a first level signal for a prescribed time, and thereafter in response to a control signal generates a second level signal, said signal transmission circuit generates an output signal and complementary signals based on said first and second level signals, and said normal operation detecting circuit detects an expiration of said prescribed time based on said complementary signals, and generates said control signal.
Claim 10
Dependent Claim
104 words
A semiconductor integrated circuit device having an internal circuit node reset signal generation circuit comprising: a power on reset signal generation circuit; a signal transmission circuit; and a normal operation detecting circuit, wherein said power on reset signal generation circuit generates a first level signal for a prescribed time, and thereafter in response to a control signal generates a second level signal, said signal transmission circuit generates an output signal and complementary signals based on said first and second level signals, and said normal operation detecting circuit detects an expiration of said prescribed time based on said complementary signals, and generates said control signal.
Claim 11
Dependent Claim
31 words
The semiconductor integrated circuit device as set forth in claim 7, further comprising a delay circuit connected between said normal operation detecting circuit and said power on reset signal generation circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-30 | 2001-09-29 | 2002-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-30 | 2005-09-29 | 2006-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-30 | 2009-09-29 | 2010-03-31 | $7700.00 | Window Closed / Lapsed |