US5734274A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fuse-programmable method and apparatus for preventing a semiconductor device from operating at speed greater than an approved speed
Assignee: Intel Corp
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Filing: 1996-03-11
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Granted: 1998-03-31
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Expires: 2016-03-11
Abstract
Abstract A clock frequency limiting circuit is disclosed. The clock frequency limiting circuit allows a semiconductor device to be fabricated, packaged and tested before the maximum clock frequency is set. The maximum clock frequency is set by burning a bank of on-chip fuses. The clock frequency limiting circuit counts clock cycles of an applied clock signal for a predetermined amount of time. A comparator compares the maximum clock frequency in the fuse bank and the counted clock cycles. A violation "kill" signal is asserted if the counted clock cycles exceeds the set maximum clock frequency.
Inventors
- 👤 Dan Gavish
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/32; G06F11/006; G01; G01R; G01R31/00; G01R31/28; G01R31/30
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
105 words
An electrical circuit for determining if a clock signal exceeds a defined clock frequency limit, said electrical circuit comprising: a reference timing circuit for generating a timing reference; a counter circuit activated by said reference timing circuit for counting a number of clock cycles of said clock signal; a programmable speed limit logic for outputting a reference number of clock cycles as defined by said defined clock frequency limit; and a comparison circuit for comparing said number of clock cycles of said clock signal counted by said counter circuit with said reference number of clock cycles to determine if said clock frequency limit is exceeded.
Claim 2
Dependent Claim
105 words
An electrical circuit for determining if a clock signal exceeds a defined clock frequency limit, said electrical circuit comprising: a reference timing circuit for generating a timing reference; a counter circuit activated by said reference timing circuit for counting a number of clock cycles of said clock signal; a programmable speed limit logic for outputting a reference number of clock cycles as defined by said defined clock frequency limit; and a comparison circuit for comparing said number of clock cycles of said clock signal counted by said counter circuit with said reference number of clock cycles to determine if said clock frequency limit is exceeded.
Claim 3
Dependent Claim
35 words
The reference circuit as claimed in claim 1 wherein said comparison circuit outputs a violation signal to limit the operation of said semiconductor device if a speed violation occurs for a predetermined amount of time.
Claim 4
Dependent Claim
19 words
The electrical circuit as claimed in claim 1 wherein said programmable speed limit logic comprises a set of fuses.
Claim 5
Independent Claim
121 words
A method for preventing a semiconductor device from being operated at an applied clock frequency greater than an approved clock frequency limit, said method comprising the steps of: manufacturing said semiconductor device; testing said semiconductor device to determine said approved clock frequency limit; programming said approved clock frequency limit into a programmable speed limit logic; generating an applied clock signal as a timing reference within said semiconductor device; counting the number of clock cycles generated during said applied clock signal; comparing said approved clock frequency limit with said number of clock cycles counted during said applied clock signal; and generating a violation signal if said number of clock cycles counted during said applied clock signal exceeds said approved clock frequency limit.
Claim 6
Independent Claim
121 words
A method for preventing a semiconductor device from being operated at an applied clock frequency greater than an approved clock frequency limit, said method comprising the steps of: manufacturing said semiconductor device; testing said semiconductor device to determine said approved clock frequency limit; programming said approved clock frequency limit into a programmable speed limit logic; generating an applied clock signal as a timing reference within said semiconductor device; counting the number of clock cycles generated during said applied clock signal; comparing said approved clock frequency limit with said number of clock cycles counted during said applied clock signal; and generating a violation signal if said number of clock cycles counted during said applied clock signal exceeds said approved clock frequency limit.
Claim 7
Dependent Claim
56 words
The method for preventing a semiconductor device from being operated at an applied clock frequency greater than an approved clock frequency limit as claimed in claim 4 wherein said step of programming said approved clock frequency limit into said programmable speed limit logic comprises burning a set of fuses that store said approved clock frequency limit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-30 | 2001-09-29 | 2002-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-30 | 2005-09-29 | 2006-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-30 | 2009-09-29 | 2010-03-31 | $7700.00 | Window Closed / Lapsed |