US5734199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having improved test electrodes
Assignee: Panasonic Holdings Corp
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Filing: 1996-12-17
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Granted: 1998-03-31
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Expires: 2016-12-17
Abstract
Abstract The main surface of a first semiconductor chip having a first functional element is formed with first testing electrodes for testing the electrical characteristics of the first functional element and first connecting electrodes electrically connected to the first functional element. The main surface of a second semiconductor chip having a second functional element is formed with second testing electrodes for testing the electrical characteristics of the second functional element and second connecting electrodes electrically connected to the second functional element. The first semiconductor chip and the second semiconductor chip are integrated by using an insulating resin, with first bumps formed on the first connecting electrodes being bonded to third bumps formed on the second connecting electrodes.
Inventors
- 👤 Tetsuo Kawakita
- 👤 Kazuhiko Matsumura
- 👤 Ichiro Yamane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:23
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10P; H10P74/00; H10P74/23; H10P74/27; H10P74/273; H10W72/072; H10W72/20; H10W90/00; H10W72/0711; H10W72/07141; H10W72/073; H10W72/07331; H10W72/07335; H10W72/07337; H10W72/07338; H10W72/241; H10W72/245; H10W72/251; H10W72/255; H10W74/00; H10W74/10; H10W74/15; H10W90/20; H10W90/291; H10W90/701; H10W90/721; H10W90/722; H10W90/731; H10W90/732
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
312 words
A semiconductor device comprising: a first semiconductor chip having a first functional element; a second semiconductor chip having a second functional element; a first testing electrode formed on a main surface of said first semiconductor chip, said first testing electrode being for testing an electric characteristic of said first functional element; a first connecting electrode formed on the main surface of said first semiconductor chip, said first connecting electrode occupying an area smaller than the area occupied by said first testing electrode and being electrically connected to said first functional element; a second testing electrode formed on a main surface of said second semiconductor chip, said second testing electrode being for testing an electric characteristic of said second functional element; a second connecting electrode formed on the main surface of said second semiconductor chip, said second connecting electrode occupying an area smaller than the area occupied by said second testing electrode and being electrically connected to said second functional element; a first testing bump formed on said first testing electrode; a first connecting bump formed on said first connecting electrode; a second testing bump formed on said second testing electrode; and a second connecting bump formed on said second connecting electrode, wherein said first connecting bump and said second connecting bump are formed so as to face and joined to each other, whereby said first functional element and said second functional element are electrically connected to each other; said first testing bump and said second testing bump are formed so as not to face each other; said first testing bump has a greater height than said first connecting bump; said second testing bump has a greater height than said second connecting bump; and said first semiconductor chip and said second semiconductor chip are integrated by using an insulating resin interposed therebetween, with the respective main surfaces thereof being opposed to each other.
Claim 2
Dependent Claim
312 words
A semiconductor device comprising: a first semiconductor chip having a first functional element; a second semiconductor chip having a second functional element; a first testing electrode formed on a main surface of said first semiconductor chip, said first testing electrode being for testing an electric characteristic of said first functional element; a first connecting electrode formed on the main surface of said first semiconductor chip, said first connecting electrode occupying an area smaller than the area occupied by said first testing electrode and being electrically connected to said first functional element; a second testing electrode formed on a main surface of said second semiconductor chip, said second testing electrode being for testing an electric characteristic of said second functional element; a second connecting electrode formed on the main surface of said second semiconductor chip, said second connecting electrode occupying an area smaller than the area occupied by said second testing electrode and being electrically connected to said second functional element; a first testing bump formed on said first testing electrode; a first connecting bump formed on said first connecting electrode; a second testing bump formed on said second testing electrode; and a second connecting bump formed on said second connecting electrode, wherein said first connecting bump and said second connecting bump are formed so as to face and joined to each other, whereby said first functional element and said second functional element are electrically connected to each other; said first testing bump and said second testing bump are formed so as not to face each other; said first testing bump has a greater height than said first connecting bump; said second testing bump has a greater height than said second connecting bump; and said first semiconductor chip and said second semiconductor chip are integrated by using an insulating resin interposed therebetween, with the respective main surfaces thereof being opposed to each other.
Claim 3
Dependent Claim
44 words
A semiconductor device according to claim 1, further comprising a clearance adjusting bump formed on at least one of said first connecting bump and said second connecting bump for eliminating variations in the clearance between said first connecting bump and said second connecting bump.
Claim 4
Dependent Claim
18 words
A semiconductor device according to claim 2, wherein said clearance adjusting bump is made of a soft metal.
Claim 5
Dependent Claim
41 words
A semiconductor device according to claim 1, wherein said second semiconductor chip is larger than said first semiconductor chip and said second testing electrode is formed on a peripheral region of said second semiconductor chip not facing said first semiconductor chip.
Claim 6
Dependent Claim
15 words
A semiconductor device according to claim 1, wherein said bump is formed by electroless plating.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-30 | 2001-09-29 | 2002-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-30 | 2005-09-29 | 2006-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-30 | 2009-09-29 | 2010-03-31 | $7700.00 | Window Closed / Lapsed |