Multiprocessor with split transaction bus architecture for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag

Claim 3

The method of claim 1, wherein said Resource means includes a requesting processor means.

Claim 4

The method of claim 1, wherein the related system bus cycle is split into an address phase and a data phase.

Claim 5

The method of claim 3, wherein said Resource means includes a requesting processor means.

Claim 6

The method of claim 1, wherein said Cache Tag means is arranged to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.

Claim 7

In a multiprocessor computer system having split-transaction bus architecture, a method of servicing a "WRITE-MISS" by performing a Write-Allocation of a desired cache line from system memory; said multiprocessor computer system including Cache Controller means, address bus means, data bus means, system memory means, and cache tag means, said method including: causing said cache controller means to gain control of said address bus, means; causing one of said cache controller means to generate address cycle; causing other cache controllers means to snoop address for cache coherency or cycle hits; if all miss, causing said cache controller means to load cycle tag for write allocation cache line address; then causing said cache controller means to begin monitoring said data bus means for cache line transfer; then causing system memory means to gain control of said data bus means and to generate a data cycle; then causing said cache controller means to receive data transfer, to update cache tag entries, to clear cycle tag entry, and to retire bus cycle.

Claim 8

In a multiprocessor computer system having split-transaction bus architecture, a method of servicing a "WRITE-MISS" by performing a Write-Allocation of a desired cache line from system memory; said multiprocessor computer system including Cache Controller means, address bus means, data bus means, system memory means, and cache tag means, said method including: causing said cache controller means to gain control of said address bus, means; causing one of said cache controller means to generate address cycle; causing other cache controllers means to snoop address for cache coherency or cycle hits; if all miss, causing said cache controller means to load cycle tag for write allocation cache line address; then causing said cache controller means to begin monitoring said data bus means for cache line transfer; then causing system memory means to gain control of said data bus means and to generate a data cycle; then causing said cache controller means to receive data transfer, to update cache tag entries, to clear cycle tag entry, and to retire bus cycle.

Claim 9

The method of claim 6, wherein said Cache Tag means is arranged to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.

Claim 10

A computer system having "split-transaction bus" architecture, said computer system including plurality of bus module means operating with an address phase and a cycle phase, and arranged for access by prescribed resource means to facilitate "RETRY", said computer system also including; Cache Tag means and Address Compare means; said computer system being arranged so that one of said plurality of bus module means stores the address for said Resource means in Cycle Tag means; and compares subsequent address bus cycles to the contents of said Cache Tag means; and, upon a "match" sends a "RETRY" direction to any other bus module means requesting access; wherein said storing being effected when said resource means completes the address phase.

Claim 11

A computer system having "split-transaction bus" architecture, said computer system including plurality of bus module means operating with an address phase and a cycle phase, and arranged for access by prescribed resource means to facilitate "RETRY", said computer system also including; Cache Tag means and Address Compare means; said computer system being arranged so that one of said plurality of bus module means stores the address for said Resource means in Cycle Tag means; and compares subsequent address bus cycles to the contents of said Cache Tag means; and, upon a "match" sends a "RETRY" direction to any other bus module means requesting access; wherein said storing being effected when said resource means completes the address phase.

Claim 12

The system of claim 8, wherein said Resource means includes a requesting processor means.

Claim 13

The system of claim 8, wherein said Cache Tag means is arranged to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.

Claim 14

A multiprocessor computer system having split-transaction bus architecture, for servicing a "WRITE-MISS" by performing a Write-Allocation of a desired cache line from system memory; said multiprocessor computer system including a plurality of Cache Controller means, address bus means, data bus means, system memory means, and cache tag means, said system including: control means in a selected one of said cache controller means which is adapted to gain control of said address bus means, and to generate an address cycle, while other cache controller means snoop the address for cache coherency or cycle hits and all miss, whereupon said controller means loads cycle tag for write allocation cache line address, so said cache controller can begin monitoring the data bus means for cache line transfer; said multiprocessor computer system also including system memory means adapted to gain control of data bus means, to generate a data cycle; and wherein said cache controller means receives data transfer; and updates cache tag entries, while clearing cycle tag entry, and retiring bus cycle.

Claim 15

A multiprocessor computer system having split-transaction bus architecture, for servicing a "WRITE-MISS" by performing a Write-Allocation of a desired cache line from system memory; said multiprocessor computer system including a plurality of Cache Controller means, address bus means, data bus means, system memory means, and cache tag means, said system including: control means in a selected one of said cache controller means which is adapted to gain control of said address bus means, and to generate an address cycle, while other cache controller means snoop the address for cache coherency or cycle hits and all miss, whereupon said controller means loads cycle tag for write allocation cache line address, so said cache controller can begin monitoring the data bus means for cache line transfer; said multiprocessor computer system also including system memory means adapted to gain control of data bus means, to generate a data cycle; and wherein said cache controller means receives data transfer; and updates cache tag entries, while clearing cycle tag entry, and retiring bus cycle.

Claim 16

The system of claim 11, wherein said Cache Tag means is arranged to support "cacheable lock" means arranged to perform load READ, WRITE sequences, including modifications thereof.