Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
150 words
A data processing system comprising: a data bus subdivided into a plurality of independent data paths; a plurality of system components coupled to the data bus, each system component monitoring each independent data path of the data bus to determine whether that system components is to receive data transmitted via that independent data path; and an allocation control circuit coupled to the system components, the allocation control circuit allocating a transmission opportunity spanning multiple bus clock cycles to a first system component such that the first system component is enabled to transmit data via any and all of the independent data paths during the transmission opportunity, the allocation control circuit enabling the first system component to begin transmission of data over the data paths at different clock cycles of the transmission opportunity such that the plurality of system components need monitor only one independent data path per bus clock cycle.
Claim 2
Dependent Claim
150 words
A data processing system comprising: a data bus subdivided into a plurality of independent data paths; a plurality of system components coupled to the data bus, each system component monitoring each independent data path of the data bus to determine whether that system components is to receive data transmitted via that independent data path; and an allocation control circuit coupled to the system components, the allocation control circuit allocating a transmission opportunity spanning multiple bus clock cycles to a first system component such that the first system component is enabled to transmit data via any and all of the independent data paths during the transmission opportunity, the allocation control circuit enabling the first system component to begin transmission of data over the data paths at different clock cycles of the transmission opportunity such that the plurality of system components need monitor only one independent data path per bus clock cycle.
Claim 3
Dependent Claim
149 words
A data processing system comprising: a time division multiplexed (TDM) data bus, the TDM data bus being subdivided into a plurality of independent data paths; a plurality of system components coupled to the TDM data bus each system component monitoring each independent data path of the data bus to determine whether that system components is to receive data transmitted via that independent data path; and an allocation control circuit coupled to the system components, the allocation control circuit allocating a contiguous group of TDM timeslots called a bandwidth unit (BU) to a first system component, wherein the first system component is thereafter enabled to transmit data via any and all of the plurality of independent data paths, the first system component skewing transmission of data over the plurality of independent data paths such that transmission is initiated on each independent data path during a different timeslot of the BU.
Claim 4
Dependent Claim
149 words
A data processing system comprising: a time division multiplexed (TDM) data bus, the TDM data bus being subdivided into a plurality of independent data paths; a plurality of system components coupled to the TDM data bus each system component monitoring each independent data path of the data bus to determine whether that system components is to receive data transmitted via that independent data path; and an allocation control circuit coupled to the system components, the allocation control circuit allocating a contiguous group of TDM timeslots called a bandwidth unit (BU) to a first system component, wherein the first system component is thereafter enabled to transmit data via any and all of the plurality of independent data paths, the first system component skewing transmission of data over the plurality of independent data paths such that transmission is initiated on each independent data path during a different timeslot of the BU.
Claim 5
Dependent Claim
33 words
The data processing system of claim 2, wherein the allocation control circuit enables transmission of data for each independent data path of the TDM data bus during a different timeslot of the BU.
Claim 6
Dependent Claim
19 words
The data processing system of claim 2, wherein data transmission is skewed by one timeslot for each data path.
Claim 7
Independent Claim
143 words
A method for transmitting data in a data processing system that comprises a data bus subdivided into a plurality of independent data paths and a plurality of system components coupled to the data bus, each system component monitoring each independent data path of the data bus to determine whether that system components is to receive data transmitted via that independent data path, the method comprising: allocating a transmission opportunity spanning multiple bus clock cycles to a first system component such that the first system component is enabled to transmit data via any and all of the independent data paths during the transmission opportunity; and enabling the first system component to begin transmission of data over the data paths at different clock cycles of the transmission cycle such that the plurality of system components need monitor only one independent data path per clock cycle.
Claim 8
Independent Claim
143 words
A method for transmitting data in a data processing system that comprises a data bus subdivided into a plurality of independent data paths and a plurality of system components coupled to the data bus, each system component monitoring each independent data path of the data bus to determine whether that system components is to receive data transmitted via that independent data path, the method comprising: allocating a transmission opportunity spanning multiple bus clock cycles to a first system component such that the first system component is enabled to transmit data via any and all of the independent data paths during the transmission opportunity; and enabling the first system component to begin transmission of data over the data paths at different clock cycles of the transmission cycle such that the plurality of system components need monitor only one independent data path per clock cycle.