← Back to Patent Explorer
US5726090A Expired / Lapsed US ⏱️ 0.0 years remaining

Gap-filling of O3 -TEOS for shallow trench isolation

Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1997-05-01
•
Granted: 1998-03-10
•
Expires: 2017-05-01
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An improved method of gap filling shallow trench isolation with ozone-TEOS is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate. A thermal oxide layer is grown within the isolation trenches. A plasma enhanced SiH4 oxide layer is deposited over the nitride layer and over the thermal oxide layer within the isolation trenches and treated with N2 plasma. Thereafter, an ozone-TEOS layer is deposited overlying the plasma enhanced SiH4 oxide layer and filling the isolation trenches. The ozone-TEOS layer and the plasma enhanced SiH4 oxide layer are polished away stopping at the nitride layer. This completes the formation of shallow trench isolation in the fabrication of the integrated circuit device.

Inventors

  • 👤 Syun-Ming Jang
  • 👤 Ying-Ho Chen
  • 👤 Chen-Hua Yu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 22:55
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 26
Claim 1
Independent Claim 124 words
A method of manufacturing an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate; depositing a plasma enhanced SiH 4 oxide layer over said nitride layer and within said isolation trenches and treating said plasma enhanced SiH 4 oxide layer with N 2 plasma; thereafter depositing an ozone-TEOS layer overlying said plasma enhanced SiH 4 oxide layer and filling said isolation trenches; polishing away said ozone-TEOS layer and said plasma enhanced SiH 4 oxide layer stopping at said silicon nitride layer; and completing the fabrication of said integrated circuit device.
Claim 2
Independent Claim 124 words
A method of manufacturing an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate; depositing a plasma enhanced SiH 4 oxide layer over said nitride layer and within said isolation trenches and treating said plasma enhanced SiH 4 oxide layer with N 2 plasma; thereafter depositing an ozone-TEOS layer overlying said plasma enhanced SiH 4 oxide layer and filling said isolation trenches; polishing away said ozone-TEOS layer and said plasma enhanced SiH 4 oxide layer stopping at said silicon nitride layer; and completing the fabrication of said integrated circuit device.
Claim 3
Dependent Claim 28 words
The method according to claim 1 further comprising growing a thermal oxide layer within said isolation trenches before said depositing of said plasma enhanced SiH 4 oxide layer.
Claim 4
Dependent Claim 18 words
The method according to claim 2 wherein said thermal oxide layer has a thickness of about 350 Angstroms.
Claim 5
Dependent Claim 26 words
The method according to claim 1 wherein said plasma enhanced SiH 4 oxide layer is deposited to a thickness of between about 350 and 600 Angstroms.
Claim 6
Dependent Claim 43 words
The method according to claim 1 wherein said N 2 plasma treatment comprises flowing N 2 gas at 400 to 600 sccm and flowing helium at 1800 to 2200 sccm at a pressure of 1 to 2 Torr for 50 to 70 seconds.
Claim 7
Dependent Claim 19 words
The method according to claim 1 wherein said width of said isolation trenches is as small as 0.35 microns.
Claim 8
Dependent Claim 15 words
The method according to claim 1 wherein said polishing is done by chemical mechanical polishing.
Claim 9
Dependent Claim 27 words
The method according to claim 1 wherein said isolation trenches are completely filled with said ozone-TEOS layer and wherein no voids are formed within said ozone-TEOS layer.
Claim 10
Dependent Claim 42 words
The method according to claim 1 wherein said completing fabrication of said integrated circuit device comprises: etching away said silicon nitride layer; removing said pad oxide layer; and fabricating semiconductor device structures in and on said semiconductor substrate between said isolation trenches.
Claim 11
Independent Claim 149 words
A method of forming shallow trench isolation in the manufacture an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate; depositing a plasma enhanced SiH 4 oxide layer over said nitride layer and within said isolation trenches and treating said plasma enhanced SiH 4 oxide layer with N 2 plasma; thereafter depositing an ozone-TEOS layer overlying said plasma enhanced SiH 4 oxide layer and filling said isolation trenches; polishing away said ozone-TEOS layer and said plasma enhanced SiH 4 oxide layer stopping at said silicon nitride layer; etching away said nitride layer; and removing said pad oxide layer to complete said formation of said shallow trench isolation in the fabrication of said integrated circuit device.
Claim 12
Independent Claim 149 words
A method of forming shallow trench isolation in the manufacture an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate; depositing a plasma enhanced SiH 4 oxide layer over said nitride layer and within said isolation trenches and treating said plasma enhanced SiH 4 oxide layer with N 2 plasma; thereafter depositing an ozone-TEOS layer overlying said plasma enhanced SiH 4 oxide layer and filling said isolation trenches; polishing away said ozone-TEOS layer and said plasma enhanced SiH 4 oxide layer stopping at said silicon nitride layer; etching away said nitride layer; and removing said pad oxide layer to complete said formation of said shallow trench isolation in the fabrication of said integrated circuit device.
Claim 13
Dependent Claim 28 words
The method according to claim 10 further comprising growing a thermal oxide layer within said isolation trenches before said depositing of said plasma enhanced SiH 4 oxide layer.
Claim 14
Dependent Claim 18 words
The method according to claim 11 wherein said thermal oxide layer has a thickness of about 350 Angstroms.
Claim 15
Dependent Claim 26 words
The method according to claim 10 wherein said plasma enhanced SiH 4 oxide layer is deposited to a thickness of between about 350 and 600 Angstroms.
Claim 16
Dependent Claim 43 words
The method according to claim 10 wherein said N 2 plasma treatment comprises flowing N 2 gas at 400 to 600 sccm and flowing helium at 1800 to 2200 sccm at a pressure of 1 to 2 Torr for 50 to 70 seconds.
Claim 17
Dependent Claim 19 words
The method according to claim 10 wherein said width of said isolation trenches is as small as 0.35 microns.
Claim 18
Dependent Claim 15 words
The method according to claim 10 wherein said polishing is done by chemical mechanical polishing.
Claim 19
Dependent Claim 27 words
The method according to claim 10 wherein said isolation trenches are completely filled with said ozone-TEOS layer and wherein no voids are formed within said ozone-TEOS layer.
Claim 20
Dependent Claim 16 words
The method according to claim 10 wherein said completed shallow trench isolation has a smooth surface.
Claim 21
Independent Claim 148 words
A method of manufacturing an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate; growing a thermal oxide layer within said isolation trenches; depositing a plasma enhanced SiH 4 oxide layer overlying said nitride layer and overlying said thermal oxide layer within said isolation trenches and treating said plasma enhanced SiH 4 oxide layer with N 2 plasma; thereafter depositing an ozone-TEOS layer overlying said plasma enhanced SiH 4 oxide layer and filling said isolation trenches; polishing away said ozone-TEOS layer and said plasma enhanced SiH 4 oxide layer stopping at said silicon nitride layer; etching away said nitride layer; removing said pad oxide layer; and completing the fabrication of said integrated circuit device.
Claim 22
Independent Claim 148 words
A method of manufacturing an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride and said pad oxide layers into said semiconductor substrate; growing a thermal oxide layer within said isolation trenches; depositing a plasma enhanced SiH 4 oxide layer overlying said nitride layer and overlying said thermal oxide layer within said isolation trenches and treating said plasma enhanced SiH 4 oxide layer with N 2 plasma; thereafter depositing an ozone-TEOS layer overlying said plasma enhanced SiH 4 oxide layer and filling said isolation trenches; polishing away said ozone-TEOS layer and said plasma enhanced SiH 4 oxide layer stopping at said silicon nitride layer; etching away said nitride layer; removing said pad oxide layer; and completing the fabrication of said integrated circuit device.
Claim 23
Dependent Claim 43 words
The method according to claim 19 wherein said N 2 plasma treatment comprises flowing N 2 gas at 400 to 600 sccm and flowing helium at 1800 to 2200 sccm at a pressure of 1 to 2 Torr for 50 to 70 seconds.
Claim 24
Dependent Claim 19 words
The method according to claim 19 wherein said width of said isolation trenches is as small as 0.35 microns.
Claim 25
Dependent Claim 27 words
The method according to claim 19 wherein said isolation trenches are completely filled with said ozone-TEOS layer and wherein no voids are formed within said ozone-TEOS layer.
Claim 26
Dependent Claim 45 words
The method according to claim 19 wherein said completing fabrication of said integrated circuit device comprises fabricating semiconductor device structures including gate electrodes and source and drain regions and electrical connections between said device structures in and on said semiconductor substrate between said isolation trenches.

References Cited (Backward Citations)

US5459108A Cited
US5536681A Cited
US5518959A Cited
US5665635A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-03-09 2001-09-08 2002-03-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-03-09 2005-09-08 2006-03-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-03-09 2009-09-08 2010-03-10 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag