US5726074A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for manufacturing semiconductor device
Assignee: NEC Electronics Corp
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Filing: 1995-12-08
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Granted: 1998-03-10
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Expires: 2015-12-08
Abstract
Abstract In a method and an apparatus for manufacturing a semiconductor integrated circuit, including a wafer test process, an assembling process and a sorting process, electric characteristics of a plurality of semiconductor integrated circuits formed on a wafer, is measured, and then stored in a memory means together with data of the position of each semiconductor integrated circuit. The plurality of semiconductor integrated circuits on the wafer are cut into individual semiconductor integrated circuit chips. On the basis of the position data and the electric characteristics of each of the semiconductor integrated circuit chips read from the memory means, the semiconductor integrated circuit chips are classified into at least two subsets each consisting of non-defective semiconductor integrated circuit chips having the same electric characteristics different from that of products included in the other subset, and the non-defective semiconductor integrated circuit chips included in each of the at least two subsets, are packaged for each of the at least two subsets, so that the sorting is simultaneously carried out.
Inventors
- 👤 Manabu Yabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:53
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/7402; H10P74/00; H10P74/23; H10W; H10W46/00; H10P72/7416; H10W46/101; H10W46/103; H10W46/106; H10W46/201; H10W46/401; H10W46/501; H10W46/601; H10W46/603
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
205 words
A method for manufacturing a semiconductor integrated circuit, including a wafer test process, an assembling process and a sorting process, the method including the steps of: measuring electric characteristics of a plurality of semiconductor integrated circuits formed on a wafer; identifying semiconductor integrated circuits of said plurality which are non-defective; causing a memory means to store the measured electric characteristics of each of said plurality of semiconductor integrated circuits identified as non-defective together with data identifying a position of each of said plurality of the semiconductor integrated circuits identified as non-defective; cutting said plurality of semiconductor integrated circuits on said wafer into individual semiconductor integrated circuit chips; classifying said non-defective semiconductor integrated circuit chips on the basis of the respective position data and the electric characteristics of each of said non-defective semiconductor integrated circuit chips read from said memory means into at least two subsets each consisting of non-defective semiconductor integrated circuit chips having the same electric characteristics, said electric characteristics being different from that of semiconductor integrated circuit chips included in the at least one other subset; and assembling and packaging the non-defective semiconductor integrated circuit chips so that the sorting into each of the at least two subsets is carried out simultaneously therewith.
Claim 2
Independent Claim
205 words
A method for manufacturing a semiconductor integrated circuit, including a wafer test process, an assembling process and a sorting process, the method including the steps of: measuring electric characteristics of a plurality of semiconductor integrated circuits formed on a wafer; identifying semiconductor integrated circuits of said plurality which are non-defective; causing a memory means to store the measured electric characteristics of each of said plurality of semiconductor integrated circuits identified as non-defective together with data identifying a position of each of said plurality of the semiconductor integrated circuits identified as non-defective; cutting said plurality of semiconductor integrated circuits on said wafer into individual semiconductor integrated circuit chips; classifying said non-defective semiconductor integrated circuit chips on the basis of the respective position data and the electric characteristics of each of said non-defective semiconductor integrated circuit chips read from said memory means into at least two subsets each consisting of non-defective semiconductor integrated circuit chips having the same electric characteristics, said electric characteristics being different from that of semiconductor integrated circuit chips included in the at least one other subset; and assembling and packaging the non-defective semiconductor integrated circuit chips so that the sorting into each of the at least two subsets is carried out simultaneously therewith.
Claim 3
Independent Claim
214 words
A method for manufacturing a semiconductor integrated circuit, including a wafer test process, an assembling process and a sorting process, the method including the steps of: measuring electric characteristics of a plurality of semiconductor integrated circuits formed on a wafer; identifying semiconductor integrated circuits of said plurality which are non-defective; causing a memory means to store the measured electric characteristics of each of said plurality of semiconductor integrated circuits identified as non-defective together with data identifying a position of each of said plurality of the semiconductor integrated circuits identified as non-defective; cutting said plurality of semiconductor integrated circuits on said wafer into individual semiconductor integrated circuit chips; classifying said non-defective semiconductor integrated circuit chips on the basis of the respective position data and the electric characteristics of each of said non-defective semiconductor integrated circuit chips read from said memory means into at least two subsets having the same electric characteristics, said electric characteristics being different from that of semiconductor integrated circuit chips included in the at least one other subset; and assembling and packaging the non-defective semiconductor integrated circuit chips included in each of said at least two subsets, for each of said at least two subsets, so that the sorting into each of the at least two subsets is carried out simultaneously therewith.
Claim 4
Independent Claim
214 words
A method for manufacturing a semiconductor integrated circuit, including a wafer test process, an assembling process and a sorting process, the method including the steps of: measuring electric characteristics of a plurality of semiconductor integrated circuits formed on a wafer; identifying semiconductor integrated circuits of said plurality which are non-defective; causing a memory means to store the measured electric characteristics of each of said plurality of semiconductor integrated circuits identified as non-defective together with data identifying a position of each of said plurality of the semiconductor integrated circuits identified as non-defective; cutting said plurality of semiconductor integrated circuits on said wafer into individual semiconductor integrated circuit chips; classifying said non-defective semiconductor integrated circuit chips on the basis of the respective position data and the electric characteristics of each of said non-defective semiconductor integrated circuit chips read from said memory means into at least two subsets having the same electric characteristics, said electric characteristics being different from that of semiconductor integrated circuit chips included in the at least one other subset; and assembling and packaging the non-defective semiconductor integrated circuit chips included in each of said at least two subsets, for each of said at least two subsets, so that the sorting into each of the at least two subsets is carried out simultaneously therewith.
Claim 5
Dependent Claim
80 words
A method claimed in claim 2 wherein said step of measuring electric characteristics of a plurality of semiconductor integrated circuits formed on a wafer is performed in a range determined by a precision of the measurement of the electric characteristics of the packaged semiconductor integrated circuits and said step of packaging and sorting the non-defective semiconductor integrated circuit chips in each of said at least two subsets is performed on the basis of grades based on the measured electrical characteristics.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |