US5724599A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Message passing and blast interrupt from processor
Assignee: Texas Instruments Inc
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Filing: 1994-03-08
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Granted: 1998-03-03
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Expires: 2014-03-08
Abstract
Abstract The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decoder and a reset control circuit. The command circuit may generate a command word on the command word bus including at least one reset command word for resetting a data processor. The decoder decodes command words received via the command word bus and includes at least a reset command decoder for decoding a reset command word. The reset control circuit resets the data processor into a state corresponding to initial application of electrical power upon receiving a reset command word. Each command word circuit generates command words indicating a particular data processor to which it is directed. Only a predetermined subset of the data processors may send the reset command word directed to other data processors. Additional actions such as interrupts, halt and cache memory flush may be controlled via the command word. In the preferred embodiment, a single command word may be directed to plural data processors. In the preferred embodiment, the command word bus and each of the data processors are disposed on a single semiconductor chip.
Inventors
- 👤 Keith Balmer
- 👤 Karl M. Guttag
- 👤 Robert J. Gove
- 👤 Nicholas Ing-Simmons
- 👤 Iain Robertson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:23
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
235 words
A multiprocessor system comprising: a command word bus; a plurality of data processors, each data processor connected to said command word bus and including a command circuit for generating a command word on said command word bus having a first set of fields identifying a type of command and a second set of fields identifying particular ones of said plurality of processors to which that command word is directed, said command circuit generating at least one reset command word for resetting at least one of said data processors at a time other than initial application of electrical power, said command circuit of only a predetermined subset of said plurality of data processors may generate said reset command word directed to ones of said plurality of data processors other than itself, a decoder coupled to said command circuit having a command register for decoding the command word, including said reset command word, said decoder of each of said plurality of data processors detects whether said reset command word is directed to the at least one of said data processors, and a reset control circuit connected to said decoder for resetting the at least one of said data processors into a state corresponding to initial application of electrical power upon receiving a reset command word by said decoder if and only if said reset command word is directed to the at least one of said data processors.
Claim 2
Dependent Claim
235 words
A multiprocessor system comprising: a command word bus; a plurality of data processors, each data processor connected to said command word bus and including a command circuit for generating a command word on said command word bus having a first set of fields identifying a type of command and a second set of fields identifying particular ones of said plurality of processors to which that command word is directed, said command circuit generating at least one reset command word for resetting at least one of said data processors at a time other than initial application of electrical power, said command circuit of only a predetermined subset of said plurality of data processors may generate said reset command word directed to ones of said plurality of data processors other than itself, a decoder coupled to said command circuit having a command register for decoding the command word, including said reset command word, said decoder of each of said plurality of data processors detects whether said reset command word is directed to the at least one of said data processors, and a reset control circuit connected to said decoder for resetting the at least one of said data processors into a state corresponding to initial application of electrical power upon receiving a reset command word by said decoder if and only if said reset command word is directed to the at least one of said data processors.
Claim 3
Dependent Claim
28 words
The multiprocessor system of claim 1, wherein: said command circuit of any one of said plurality of data processors may generate said reset command word directed to itself.
Claim 4
Dependent Claim
176 words
The multiprocessor system of claim 1, wherein: said command circuit of at least one of said plurality of data processors further generates a halt command word indicating a particular one of said plurality of data processors whose operation is to be halted and an unhalt command word indicating a particular one of said plurality of data processors whose halted operation is to be restarted, said decoder of each of said plurality of data processors detects whether said halt command word is directed to the at least one of said data processors and whether said unhalt command word is directed to the at least one of said data processors, each of said data processors includes a halt control circuit connected to said decoder for halting operation of the at least one of said data processors if and only if said halt command word is directed to the at least one of said data processors and resuming halted operation if and only if said unhalt command word is directed to the at least one of said data processors.
Claim 5
Dependent Claim
42 words
The multiprocessor system of claim 3, wherein: said command circuit of only a predetermined subset of said plurality of data processors may generate said halt and said unhalt command words directed to ones of said plurality of data processors other than itself.
Claim 6
Dependent Claim
226 words
The multiprocessor system of claim 3, wherein: said command word bus consists of a plurality of lines; said command circuit of each of said plurality of data processors generates said command word having a number of bits equal to said plurality of lines of said command word bus, and having a first set of bits, each bit of said first set of bits corresponding to a predetermined type of command and a second set of bits, each bit of said second set of bits corresponding to a particular one of said plurality of data processors, and said decoder of each of said plurality of data processors detects whether each bit of said first set of bits of said command word has a first state or a second state, indicates performance of a single one of said types of command having a corresponding bit of said first set of bits in said first state only if said bit of said second set corresponding to the at least one of said data processors has said first state, said single one of said types of command indicated for performance selected in accordance with a predetermined hierarchy of priority if more than one bit of said first set of bits is in said first state, said decoder providing higher priority to an unhalt command type than a halt command type.
Claim 7
Dependent Claim
165 words
The multiprocessor system of claim 1, wherein: each of said data processors includes an instruction cache memory; said command circuit of each of said plurality of data processors further generates an instruction cache flush command word indicating a particular one of said plurality of data processors is to flush its instruction cache memory, said command circuit of only a predetermined subset of said plurality of data processors may generate said instruction cache flush command word directed to ones of said plurality of data processors other than itself, said decoder of each of said plurality of data processors detects whether said instruction cache command word is directed to the at least one of said data processors, each of said plurality of data processors includes an instruction cache flush control circuit connected to said decoder and to said instruction cache memory for flushing said corresponding instruction cache memory only if said instruction cache flush command word is directed to the at least one of said data processors.
Claim 8
Dependent Claim
30 words
The multiprocessor system of claim 6, wherein: said command circuit of any one of said plurality of data processors may generate said instruction cache flush command word directed to itself.
Claim 9
Dependent Claim
165 words
The multiprocessor system of claim 1, wherein: at least one of said data processors includes a data cache memory; said command circuit of each of said plurality of data processors further generates a data cache flush command word indicating a particular one of said plurality of data processors is to flush its data cache memory, said command circuit of only a predetermined subset of said plurality of data processors may generate said data cache flush command word directed to ones of said plurality of data processors other than itself, said decoder of each of said plurality of data processors detects whether said data cache flush command word is directed to the at least one of said data processors, each of said data processors includes a data cache flush control circuit connected to said decoder and to said data cache memory for flushing said corresponding data cache memory if said data cache flush command word is directed to the at least one of said data processors.
Claim 10
Dependent Claim
41 words
The multiprocessor system of claim 1, wherein: said command circuit of each of said plurality of data processors generates said command word including a field indicating particular ones of said plurality of data processors to which said command word is directed.
Claim 11
Dependent Claim
41 words
The multiprocessor system of claim 9, wherein: said command circuit of each of said plurality of data processors generates said command word including an indication of plural ones of said plurality of data processors to which said command word is directed.
Claim 12
Dependent Claim
26 words
The multiprocessor system of claim 1, wherein: said command word bus and each of said plurality of data processors are disposed on a single semiconductor chip.
Claim 13
Dependent Claim
196 words
The multiprocessor system of claim 1, wherein: said command word bus consists of a plurality of lines; said command circuit of each of said plurality of data processors generates said command word having a number of bits equal to said plurality of lines of said command word bus, and having a first set of bits, each bit of said first set of bits corresponding to a predetermined type of command and a second set of bits, each bit of said second set corresponding to a particular one of said plurality of data processors, and said decoder of each of said plurality of data processors detects whether each bit of said first set of bits of said command word has a first state or a second state and detects whether said bit of said second set corresponding to the at least one of said data processors has a first state or second state, and indicates performance of each type of command having a corresponding bit of said first set of bits in said first state only if said bit of said second set corresponding to the at least one of said data processors has said first state.
Claim 14
Dependent Claim
100 words
The multiprocessor system of claim 12, wherein: said decoder of each of said plurality of data processors indicates performance of a single one of said types of command having a corresponding bit of said first set of bits in said first state only if said bit of said second set corresponding to the at least one of said data processors has said first state, said single one of said types of command indicated for performance selected in accordance with a predetermined hierarchy of priority if more than one bit of said first set of bits is in said first state.
Claim 15
Dependent Claim
27 words
The multiprocessor system of claim 13, wherein: said decoder provides a highest priority among said command types to resetting the at least one of said data processors.
Claim 16
Dependent Claim
244 words
A data processor system comprising: a system memory; and a multiprocessor circuit including a command word bus; a plurality of data processors, each data processor connected to said command word bus and including a command circuit for generating a command word on said command word bus having a first set of fields identifying a type of command and a second set of fields identifying particular ones of said plurality of processors to which that command word is directed, said command circuit generating at least one reset command word for resetting at least one of said data processors at a time other than initial application of electrical power, said command circuit of only a predetermined subset of said plurality of data processors may generate said reset command word directed to ones of said plurality of data processors other than itself, a decoder coupled to said command circuit having a command register for decoding the command word, including said reset command word, said decoder of each of said plurality of data processors detects whether said reset command word is directed to the at least one of said data processors, and a reset control circuit connected to said decoder for resetting the at least one of said data processors into a state corresponding to initial application of electrical power upon receiving a reset command word by said decoder if and only if said reset command word is directed to the at least one of said data processors.
Claim 17
Dependent Claim
244 words
A data processor system comprising: a system memory; and a multiprocessor circuit including a command word bus; a plurality of data processors, each data processor connected to said command word bus and including a command circuit for generating a command word on said command word bus having a first set of fields identifying a type of command and a second set of fields identifying particular ones of said plurality of processors to which that command word is directed, said command circuit generating at least one reset command word for resetting at least one of said data processors at a time other than initial application of electrical power, said command circuit of only a predetermined subset of said plurality of data processors may generate said reset command word directed to ones of said plurality of data processors other than itself, a decoder coupled to said command circuit having a command register for decoding the command word, including said reset command word, said decoder of each of said plurality of data processors detects whether said reset command word is directed to the at least one of said data processors, and a reset control circuit connected to said decoder for resetting the at least one of said data processors into a state corresponding to initial application of electrical power upon receiving a reset command word by said decoder if and only if said reset command word is directed to the at least one of said data processors.
Claim 18
Dependent Claim
29 words
The data processor system of claim 15, wherein: said command circuit of any one of said plurality of data processors may generate said reset command word directed to itself.
Claim 19
Dependent Claim
177 words
The data processor system of claim 15, wherein: said command circuit of each of said plurality of data processors further generates a halt command word indicating a particular one of said plurality of data processors whose operation is to be halted and an unhalt command word indicating a particular one of said plurality of data processors whose halted operation is to be restarted, said decoder of each of said plurality of data processors detects whether said halt command word is directed to the at least one of said data processors and whether said unhalt command word is directed to the at least one of said data processors, each of said plurality of data processors includes an halt control circuit connected to said decoder for halting operation of the at least one of said data processors if and only if said halt command word is directed to the at least one of said data processors and resuming halted operation if and only if said unhalt command word is directed to the at least one of said data processors.
Claim 20
Dependent Claim
43 words
The data processor system of claim 17, wherein: said command circuit of only a predetermined subset of said plurality of data processors may generate said halt and said unhalt command words directed to ones of said plurality of data processors other than itself.
Claim 21
Dependent Claim
227 words
The data processor system of claim 17, wherein: said command word bus consists of a plurality of lines; said command circuit of each of said plurality of data processors generates said command word having a number of bits equal to said plurality of lines of said command word bus, and having a first set of bits, each bit of said first set of bits corresponding to a predetermined type of command and a second set of bits, each bit of said second set of bits corresponding to a particular one of said plurality of data processors, and said decoder of each of said plurality of data processors detects whether each bit of said first set of bits of said command word has a first state or a second state, indicates performance of a single one of said types of command having a corresponding bit of said first set of bits in said first state only if said bit of said second set corresponding to the at least one of said data processors has said first state, said single one of said types of command indicated for performance selected in accordance with a predetermined hierarchy of priority if more than one bit of said first set of bits is in said first state, said decoder providing higher priority to an unhalt command type than a halt command type.
Claim 22
Dependent Claim
165 words
The data processor system of claim 15, wherein: each of said plurality of data processors includes an instruction cache memory; said command circuit of each of said plurality of data processors further generates an instruction cache flush command word indicating a particular one of said plurality of data processors is to flush its instruction cache memory, said command circuit of only a predetermined subset of said plurality of data processors may generate said instruction cache flush command word directed to ones of said plurality of data processors other than itself, said decoder of each of said plurality of data processors detects whether said instruction cache command word is directed to the at least one of said data processors, each of said data processors includes an instruction cache flush control circuit connected to said decoder and to said instruction cache memory for flushing said instruction cache memory only if said instruction cache flush command word is directed to the at least one of said data processors.
Claim 23
Dependent Claim
31 words
The data processor system of claim 20, wherein: said command circuit of any one of said plurality of data processors may generate said instruction cache flush command word directed to itself.
Claim 24
Dependent Claim
168 words
The data processor system of claim 15, wherein: at least one of said plurality of data processors includes a data cache memory; said command circuit of each of said plurality of data processors further generates a data cache flush command word indicating a particular one of said plurality of data processors is to flush its data cache memory, said command circuit of only a predetermined subset of said plurality of data processors may generate said data cache flush command word directed to ones of said plurality of data processors other than itself, said decoder of each of said plurality of data processors detects whether said data cache flush command word is directed to the at least one of said data processors, each of said data processors includes a data cache flush control circuit connected to said decoder and to said data cache memory for flushing said corresponding data cache memory if said data cache flush command word is directed to the at least one of said data processors.
Claim 25
Dependent Claim
42 words
The data processor system of claim 15, wherein: said command circuit of each of said plurality of data processors generates said command word including a field indicating particular ones of said plurality of data processors to which said command word is directed.
Claim 26
Dependent Claim
42 words
The data processor system of claim 23, wherein: said command circuit of each of said plurality of data processors generates said command word including an indication of plural ones of said plurality of data processors to which said command word is directed.
Claim 27
Dependent Claim
27 words
The data processor system of claim 15, wherein: said command word bus and each of said plurality of data processors are disposed on a single semiconductor chip.
Claim 28
Dependent Claim
197 words
The data processor system of claim 15, wherein: said command word bus consists of a plurality of lines; said command circuit of each of said plurality of data processors generates said command word having a number of bits equal to said plurality of lines of said command word bus, and having a first set of bits, each bit of said first set of bits corresponding to a predetermined type of command and a second set of bits, each bit of said second set corresponding to a particular one of said plurality of data processors, and said decoder of each of said plurality of data processors detects whether each bit of said first set of bits of said command word has a first state or a second state and detects whether said bit of said second set corresponding to the at least one of said data processors has a first state or second state, and indicates performance of each type of command having a corresponding bit of said first set of bits in said first state only if said bit of said second set corresponding to the at least one of said data processors has said first state.
Claim 29
Dependent Claim
101 words
The data processor system of claim 26, wherein: said decoder of each of said plurality of data processors indicates performance of a single one of said types of command having a corresponding bit of said first set of bits in said first state only if said bit of said second set corresponding to the at least one of said data processors has said first state, said single one of said types of command indicated for performance selected in accordance with a predetermined hierarchy of priority if more than one bit of said first set of bits is in said first state.
Claim 30
Dependent Claim
28 words
The data processor system of claim 27, wherein: said decoder provides a highest priority among said command types to resetting the at least one of said data processors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |