Method and apparatus for independently resetting processors and cache controllers in multiple processor systems

Claim 2

A computer system comprising: a system bus for transmitting program instructions and data; a primary processor connected to said system bus for controlling said system bus and for executing program instructions; at least one secondary processor connected to said system bus for controlling said system bus and for executing program instructions; means for generating a system reset signal; means responsive to said system reset signal for resetting all of said primary and secondary processors; means for generating a primary processor reset signal including: means for receiving program instructions and data via said system bus; decoding means for decoding said program instructions to determine that a primary processor reset has been requested, said decoding means including: a primary processor reset data register; means for generating a register select signal for enabling said primary processor reset data register to receive data in response to primary processor reset program instructions; and means for writing reset data indicative of a primary processor reset request to said primary processor reset data register; and reset signal means responsive to said decoding means determining that a primary processor reset has been requested for generating said primary processor reset signal, said reset signal means comprising: means responsive to the state of data in said primary processor reset data register for generating a primary processor reset initiation signal; means responsive to said primary processor reset initiation signal for generating a processor hold request signal; means for providing the processor hold request to said primary processor; means for delaying the generation of said primary processor reset signal until said primary processor is in a hold state; and means for providing said primary processor reset signal after said primary processor is in a hold state; and means responsive to said primary processor reset signal for resetting only said primary processor.

Claim 3

The computer system of claim 1, further comprising: reset timing means coupled to said means for providing said primary processor reset signal for maintaining said primary processor reset signal active for a specified period.

Claim 4

The computer system of claim 2, wherein said reset timing means comprises: a counter circuit activated by the initiation of said primary processor reset signal; and means associated with said counter circuit, for deactivating said primary processor reset signal after said specific time period has elapsed.

Claim 5

The computer system of claim 1, further comprising: means associated with each secondary processor for generating a secondary processor only reset signal; means associated with each secondary processor and responsive to said secondary processor only reset signal of that secondary processor for resetting only said associated secondary processor.

Claim 6

The computer system of claim 1, further comprising: means for generating a processor reset signal to reset said primary and all secondary processors in response to a system shutdown condition.

Claim 7

A computer system comprising: a processor; system main memory for storing data and coded instructions; a processor bus connected to said processor; a system bus for transmitting program instructions, data and control signals; cache memory connected to said processor bus and said system main memory for temporarily storing a duplication of a portion of the data and program instructions stored in said system main memory for high speed access by said processor; a cache memory controller connected to said processor bus, said processor, said cache memory, said system main memory and said system bus for determining whether program instructions or data required by said processor are resident in cache memory; means for generating a system reset signal; means responsive to said system reset signal for resetting said processor and said cache controller; means responsive to program instructions provided over said system bus for generating a processor reset signal, said means for generating a processor reset signal including: means for receiving program instructions and data via said system bus; decoding means for decoding program instructions to determine that a processor reset has been requested, said decoding means including: a processor reset data register; means responsive to said decoding circuit for enabling said processor reset register to receive data in response to processor reset instructions; and means for writing data indicative of a processor reset request to said processor reset register; and reset signal means responsive to said decoding means determining that a processor reset has been requested for generating said processor reset signal, said reset signal means comprising: means responsive to the state of data in said processor reset data register for generating a processor reset initiation signal; means responsive to said reset initiation signal for generating a processor hold request signal; means for providing said processor hold request signal to said processor; means for delaying the generation of a processor reset signal until said processor is in a hold state; and means for providing said processor reset signal after said processor is in a hold state; and means responsive to said processor reset signal for resetting said processor only.

Claim 8

A computer system comprising: a processor; system main memory for storing data and coded instructions; a processor bus connected to said processor; a system bus for transmitting program instructions, data and control signals; cache memory connected to said processor bus and said system main memory for temporarily storing a duplication of a portion of the data and program instructions stored in said system main memory for high speed access by said processor; a cache memory controller connected to said processor bus, said processor, said cache memory, said system main memory and said system bus for determining whether program instructions or data required by said processor are resident in cache memory; means for generating a system reset signal; means responsive to said system reset signal for resetting said processor and said cache controller; means responsive to program instructions provided over said system bus for generating a processor reset signal, said means for generating a processor reset signal including: means for receiving program instructions and data via said system bus; decoding means for decoding program instructions to determine that a processor reset has been requested, said decoding means including: a processor reset data register; means responsive to said decoding circuit for enabling said processor reset register to receive data in response to processor reset instructions; and means for writing data indicative of a processor reset request to said processor reset register; and reset signal means responsive to said decoding means determining that a processor reset has been requested for generating said processor reset signal, said reset signal means comprising: means responsive to the state of data in said processor reset data register for generating a processor reset initiation signal; means responsive to said reset initiation signal for generating a processor hold request signal; means for providing said processor hold request signal to said processor; means for delaying the generation of a processor reset signal until said processor is in a hold state; and means for providing said processor reset signal after said processor is in a hold state; and means responsive to said processor reset signal for resetting said processor only.