Patent US3502575A successfully refreshed from Google Patents.
EP0191402A2
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Data processing system
Assignee: Toshiba Corp
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Filing: 1986-02-04
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Granted: —
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Expires: 2006-02-04
Abstract
Abstract This data processing system has different kinds of microprocessors (12A, 12B, 12C), a memory bus (MB), a memory (14) which is connected to the microprocessors (12A, 12B, 12C) through the memory bus (MB), and a control circuit to se- llectively activate one of the microprocessors (12A, 12B, 12C). A feature of the control circuit of this data processing system is that it has a selection controller (26) in which a selection data item is set by the active one of the microprocessors (12A, 12B, 12C) and a selector (28) for supplying rest mode signals to the microprocessors excluding the one microprocessor corresponding to the content of the selection controller (26).
Inventors
- 👤 Keiji Namimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 15:43
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/24
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
212 words
A data processing system comprising: different kinds of processing units (12A-12C, 24A-24C) each of which has an input terminal for receiving a rest mode signal and each of which is made inoperative in response to the rest mode signal and is active when the rest mode signal is not supplied; bus means (MB) having address, data and control busses (AB, DB and CB) for respectively transferring address, data and control signal; memory means (14 and 20), connected to said processing units (12A-12C, 24A-24C), which stores a plurality of execution programs to be respectively executed by said processing units (12A-12C, 24A-24C); and selection control means connected to said processing units (12A-12C, 24A-24C) for selectively activating said processing units (12A-12C, 24A-24C); characterized in that said selection control means includes a selection control section (26, 28 and 30), having at least one specified address and connected to said processing units (12A-12C, 24A-24C) through said bus means (MB), which receives and stores selection data in response to an address selection effected by the active unit of said processing units (12A-12C, 24A-24C) and supplies the rest mode signal to all input terminals of said processing units (12A-12C, 24A-24C) except the one designated by the stored selection data, said selection data being generated from said active processing unit.
Claim 2
Dependent Claim
212 words
A data processing system comprising: different kinds of processing units (12A-12C, 24A-24C) each of which has an input terminal for receiving a rest mode signal and each of which is made inoperative in response to the rest mode signal and is active when the rest mode signal is not supplied; bus means (MB) having address, data and control busses (AB, DB and CB) for respectively transferring address, data and control signal; memory means (14 and 20), connected to said processing units (12A-12C, 24A-24C), which stores a plurality of execution programs to be respectively executed by said processing units (12A-12C, 24A-24C); and selection control means connected to said processing units (12A-12C, 24A-24C) for selectively activating said processing units (12A-12C, 24A-24C); characterized in that said selection control means includes a selection control section (26, 28 and 30), having at least one specified address and connected to said processing units (12A-12C, 24A-24C) through said bus means (MB), which receives and stores selection data in response to an address selection effected by the active unit of said processing units (12A-12C, 24A-24C) and supplies the rest mode signal to all input terminals of said processing units (12A-12C, 24A-24C) except the one designated by the stored selection data, said selection data being generated from said active processing unit.
Claim 3
Dependent Claim
30 words
A data processing system according to claim 1, characterized in that said memory means (14 and 20) is connected to said processing units (12A-12C, 24A-24C) through said bus means (MB).
Claim 4
Dependent Claim
92 words
A data processing system according to claim 1, characterized in that said selection control section includes a register circuit (34) for storing the selection data, a selector circuit (28) connected to said register circuit (34) for decoding the content of said register circuit (34) to supply said rest mode signal to the input terminals of the unselected processing units, and an address circuit connected to said bus means (MB) which responds to the specified address signal and allows said register circuit (34) to store the selection data from said active processing unit.
Claim 5
Dependent Claim
44 words
A data processing system according to claim 3, characterized in that said selection control section includes a reset circuit (30) for setting into said register circuit (34) the selection data designating a predetermined one of said processing units (12A-12C, 24A-24C), upon application of power.
Claim 6
Dependent Claim
54 words
A data processing system according to claim 4, characterized in that said memory means includes a disk memory section (20) storing said execution programs and a main memory section (14) into which one of the execution programs is selectively loaded from said disk memory section (20) under the control of the active processing unit.
Claim 7
Dependent Claim
56 words
A data processing system according to claim 5, characterized in that said main memory section includes a RAM (14A) and a ROM (14B) storing a loader program which is executed by said predetermined processing unit to load into said RAM (14A) the execution program to be executed by the same processing unit after the loading operation.
Claim 8
Dependent Claim
30 words
A data processing system according to claim 6, characterized in that said processing units respectively include microprocessors (12A-12C) each having the same type of reset terminal as said input terminal.
Claim 9
Dependent Claim
46 words
A data processing system according to claim 7, characterized in that said processing units respectively include buffer circuits (24A-24C) connected between said microprocessors (12A-12C) and bus means (MB) for electrically separating the corresponding microprocessor from said bus means (MB) in response to the rest mode signal.
Claim 10
Dependent Claim
25 words
A data processing system according to claim 8, characterized in that said execution programs each are one of self assembler program and self compiler program.
Claim 11
Dependent Claim
94 words
A data processing system according to claim 1, characterized in that said selection control section includes a register circuit having a plurality of 1-bit registers respectively connected to the input terminals of said processing units (12A-12C, 24A-24C) for storing the selection data to supply said rest mode signal to the input terminals of the unselected processing units and an address circuit connected to said bus means (MB) which responds to the specified address signals corresponding to said 1-bit registers and allows said 1-bit registers to store the selection data from said active processing unit.
Claim 12
Dependent Claim
43 words
A data processing system according to claim 10, characterized in that said selection control section includes a reset circuit (30) for setting into said register circuit the selection data designating a predetermined one of said processing units (12A-12C, 24A-24C), upon application of power.
References Cited (Backward Citations)
JPS58129673A
Cited
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