Method for measuring architectural test coverage for design verification and building conformal test

Claim 2

A computer-implemented method of generating test vectors for hardware design verification, having a behavioral simulator model representing an architecture corresponding to the hardware design, the method comprising the steps of: generating said behavioral simulator model, said model comprising a plurality of conditional branch statements and logical function statements conditional thereon; generating a set of test input cases corresponding to said behavioral simulator model; receiving and storing a test coverage criteria, said test coverage criteria establishing a criteria which an execution of a sub-plurality of said conditional branch statements and of said function statements must meet to constitute an execution of said behavioral simulator model; generating a plurality of logical coverage tasks, each of said logical coverage tasks having an executable sub-plurality of said conditional branch statements and said logical function statements, and each of said plurality of tasks being in accordance with said received test coverage criteria; for each test input case in said set of test input cases, selecting the test input case and executing the selected test input case on the behavioral simulator model; determining which of said plurality of logical coverage tasks are executed by each test input case executed on the behavioral simulator model; and identifying all of the logical coverage tasks of the behavioral simulator model that were not executed by the test input cases, based on a repeating of said determining step for each test input case.

Claim 3

A method as in claim 1 wherein the test coverage criteria is one or more of statement coverage, branch coverage, and path coverage.

Claim 4

A method as in claim 1, wherein the test coverage criteria is data flow coverage.

Claim 5

A method as in claim 1, wherein the test coverage criteria is mutation coverage.

Claim 6

A method according to claim 1, further including the steps of: identifying all test input cases that cause execution cover any of the plurality of logical coverage tasks; and generating a reduced set of test input cases based on the test input cases identified by said identifying step.

Claim 7

A programmable computer operable for performing a method of measuring architectural test coverage for hardware design verification, wherein a behavioral simulator model represents an architecture corresponding to the hardware design, comprising: means for generating said behavioral simulator model, said model comprising a plurality of conditional branch statements and logical function statements conditional thereon; means for generating a set of test input cases corresponding to said behavioral simulator model; means for receiving and storing a test coverage criteria, said test coverage criteria establishing a criteria which an execution of a sub-plurality of said conditional branch statements and of said function statements must meet to constitute an execution of said behavioral simulator model; means for generating a plurality of logical tasks, each of said logical tasks having an executable sub-plurality of said conditional branch statements and said logical function statements, and each of said plurality of tasks being in accordance with said received test coverage criteria means for selecting each test input case in said set of test input cases and executing said selected test input case on the behavioral simulator model; means for determining which of said plurality of logical coverage tasks are executed by each test input case executed on the behavioral simulator model; and means for identifying all of said input test cases that cause execution of any of the plurality of tasks based on an output of said means for determining; and means for producing a reduced test set consisting of all of the test input cases that cause execution of any of the plurality of tasks, based on an output of said means for identifying.

Claim 8

A programmable computer operable for performing a method of measuring architectural test coverage for hardware design verification, wherein a behavioral simulator model represents an architecture corresponding to the hardware design, comprising: means for generating said behavioral simulator model, said model comprising a plurality of conditional branch statements and logical function statements conditional thereon; means for generating a set of test input cases corresponding to said behavioral simulator model; means for receiving and storing a test coverage criteria, said test coverage criteria establishing a criteria which an execution of a sub-plurality of said conditional branch statements and of said function statements must meet to constitute an execution of said behavioral simulator model; means for generating a plurality of logical tasks, each of said logical tasks having an executable sub-plurality of said conditional branch statements and said logical function statements, and each of said plurality of tasks being in accordance with said received test coverage criteria means for selecting each test input case in said set of test input cases and executing said selected test input case on the behavioral simulator model; means for determining which of said plurality of logical coverage tasks are executed by each test input case executed on the behavioral simulator model; and means for identifying all of said input test cases that cause execution of any of the plurality of tasks based on an output of said means for determining; and means for producing a reduced test set consisting of all of the test input cases that cause execution of any of the plurality of tasks, based on an output of said means for identifying.

Claim 9

A computer-implemented method of generating test vectors for hardware design verification, having a behavioral simulator model representing an architecture corresponding to the hardware design, comprising the steps of: generating said behavioral simulator model, said model comprising a plurality of conditional branch statements and logical function statements conditional thereon; generating a set of test input cases corresponding to said behavioral simulator model; receiving and storing a test coverage criteria, said test coverage criteria establishing a criteria which an execution of a sub-plurality of said conditional branch statements and of said function statements must meet to constitute an execution of said behavioral simulator model; generating a plurality of logical coverage tasks, each of said logical coverage tasks having an executable sub-plurality of said conditional branch statements and said logical function statements, and each of said plurality of tasks being in accordance with said received test coverage criteria; initializing all of said logical coverage tasks to a condition of having not been executed; and repeating the steps of (1) selecting a test input case and executing the selected test input case on the behavioral simulator model, and (2) determining whether any of said plurality of logical coverage tasks are executed by the selected test input case for a first time subsequent to said initializing step and, if any are so executed for a first time, determining which of the test input cases are so executed, until all of said plurality of logical coverage tasks are executed or all of said test input cases are selected and executed, whichever occurs first.

Claim 10

A computer-implemented method of generating test vectors for hardware design verification, having a behavioral simulator model representing an architecture corresponding to the hardware design, comprising the steps of: generating said behavioral simulator model, said model comprising a plurality of conditional branch statements and logical function statements conditional thereon; generating a set of test input cases corresponding to said behavioral simulator model; receiving and storing a test coverage criteria, said test coverage criteria establishing a criteria which an execution of a sub-plurality of said conditional branch statements and of said function statements must meet to constitute an execution of said behavioral simulator model; generating a plurality of logical coverage tasks, each of said logical coverage tasks having an executable sub-plurality of said conditional branch statements and said logical function statements, and each of said plurality of tasks being in accordance with said received test coverage criteria; initializing all of said logical coverage tasks to a condition of having not been executed; and repeating the steps of (1) selecting a test input case and executing the selected test input case on the behavioral simulator model, and (2) determining whether any of said plurality of logical coverage tasks are executed by the selected test input case for a first time subsequent to said initializing step and, if any are so executed for a first time, determining which of the test input cases are so executed, until all of said plurality of logical coverage tasks are executed or all of said test input cases are selected and executed, whichever occurs first.

Claim 11

A method according to claim 7, further comprising the step of identifying all of said plurality of test input cases which cause any of said plurality of logical coverage tasks to be executed for a first time, based on said determining step.