Abstract A self-refreshable dual port dynamic CAM cell which performs a self-refresh operation with no effect on a data read operation and no reduction in performance. The dynamic CAM cell comprises first and second MOS transistors for storing first true and complementary bit data from first true and complementary bit lines, respectively, third and fourth MOS transistors for transferring the data stored in the first and second MOS transistors to a match line in response to the first true and complementary bit data from the first true and complementary bit lines, respectively, a fifth MOS transistor for storing the first true bit data from the first true bit line into the first MOS transistor in response to a signal from a first word line, a sixth MOS transistor for storing the first complementary bit data from the first complementary bit line into the second MOS transistor in response to the signal from the first word line, a seventh MOS transistor for refreshing the data stored in the first MOS transistor with second true bit data from a second true bit line in response to a signal from a second word line, and an eighth MOS transistor for refreshing the data stored in the second MOS transistor with second complementary bit data from a second complementary bit line in response to the signal from the second word line.
A dynamic CAM cell array refreshing circuit comprising: a dynamic CAM cell array including a plurality of self-refreshable dual port dynamic CAM cells; first word line drive means for generating write addresses to drive first word lines of said dynamic CAM cell array to store initial data into said dynamic CAM cell array; refresh word line drive means for generating addresses to drive second word lines of said dynamic CAM cell array to refresh said dynamic CAM cell array; clock generation means for generating a clock necessary to a refresh operation; refresh control means for adjusting the clock from said clock generation means according to an initial data write mode and a normal operation mode and supplying the adjusted clock to said refresh word line drive means; refresh sense amplification means for sensing data on a bit line of each of said plurality of dynamic CAM cells in said dynamic CAM cell array and refreshing the sensed data; and data input means for supplying data to be stored in said dynamic CAM cell array and data to be compared therewith to said dynamic CAM cell array.
Claim 2
Dependent Claim
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A dynamic CAM cell array refreshing circuit comprising: a dynamic CAM cell array including a plurality of self-refreshable dual port dynamic CAM cells; first word line drive means for generating write addresses to drive first word lines of said dynamic CAM cell array to store initial data into said dynamic CAM cell array; refresh word line drive means for generating addresses to drive second word lines of said dynamic CAM cell array to refresh said dynamic CAM cell array; clock generation means for generating a clock necessary to a refresh operation; refresh control means for adjusting the clock from said clock generation means according to an initial data write mode and a normal operation mode and supplying the adjusted clock to said refresh word line drive means; refresh sense amplification means for sensing data on a bit line of each of said plurality of dynamic CAM cells in said dynamic CAM cell array and refreshing the sensed data; and data input means for supplying data to be stored in said dynamic CAM cell array and data to be compared therewith to said dynamic CAM cell array.