US5724277A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Background noise generating apparatus
Assignee: NEC Corp
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Filing: 1995-12-06
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Granted: 1998-03-03
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Expires: 2015-12-06
Abstract
Abstract An object of the invention is to provide a background noise generating circuit having a small circuit scale and a small power consumption and capable of setting an arbitrary gain for the background noise. For each frame clock, a circuit (6, 5) generates a gain setting code signal S5 in synchronism with a data clock, and a random generator 21 generates a random number S21 in synchronism with a frame clock FCK. For a period of each frame, a logic gate 22 generates an exclusive-OR between the gain setting code signal S5 and the random number S21, the exclusive-OR constituting a background noise signal S9, which is supplied to a signal processing circuit 7 through a selection circuit 4 during a background noise period. Th gain setting code signal S5 may be determined by detecting the level of a received signal during a received signal input period just before the background noise period, and the gain setting code signal S5 thus determined is held during the background noise period and continues to be supplied to the logic gate.
Inventors
- 👤 Masashi Nakagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:19
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A background noise generating apparatus comprising: a first input circuit for receiving a level control information; a level control circuit receiving an output of said first input circuit and controlled by a first clock so as to output a level control signal in accordance with said output of said first input circuit; a random number generator receiving a second clock different from said first clock, for generating a random data; a logic gate receiving said random data and said level control signal during a first period in accordance with said second clock, for generating a predetermined logic value signal; a selection controller, receiving said second clock, for outputting a predetermined selection control signal in synchronism with said second clock; and a selection circuit for receiving said logic value signal outputted from said logic gate, for selectively supplying said logic value signal of said logic gate during said first period in accordance with said selection control signal from said selection controller.
Claim 2
Dependent Claim
160 words
A background noise generating apparatus comprising: a first input circuit for receiving a level control information; a level control circuit receiving an output of said first input circuit and controlled by a first clock so as to output a level control signal in accordance with said output of said first input circuit; a random number generator receiving a second clock different from said first clock, for generating a random data; a logic gate receiving said random data and said level control signal during a first period in accordance with said second clock, for generating a predetermined logic value signal; a selection controller, receiving said second clock, for outputting a predetermined selection control signal in synchronism with said second clock; and a selection circuit for receiving said logic value signal outputted from said logic gate, for selectively supplying said logic value signal of said logic gate during said first period in accordance with said selection control signal from said selection controller.
Claim 3
Dependent Claim
23 words
A background noise generating apparatus claimed in claim 1, wherein said first clock has a period shorter than that of said second clock.
Claim 4
Dependent Claim
27 words
A background noise generating apparatus claimed in claim 1, wherein said logic gate comprises an exclusive-OR gate for receiving said random data and said level control signal.
Claim 5
Dependent Claim
97 words
A background noise generating apparatus claimed in claim 1, further including a second input circuit for receiving a predetermined input signal in response to said first clock, and a signal processing circuit for receiving an output signal outputted from said selection circuit, said selection circuit also for receiving an output signal outputted from said second input circuit, said selection circuit being controlled in accordance with said selection control signal, so as to selectively supply said output signal outputted from said second input circuit, to said signal processing circuit during a second period different from said first period.
Claim 6
Dependent Claim
65 words
A background noise generating apparatus claimed in claim 4, wherein said output of said second input circuit is serially outputted in response to said first clock, and said level control signal of said level control circuit is also serially outputted in response to said first clock, and wherein said random data of said random number generator is serially outputted in response to said second clock.
Claim 7
Dependent Claim
75 words
A background noise generating apparatus claimed in claim 1, wherein said level control circuit includes: a detection circuit, connected to said output of said selection circuit, for detecting said level of said output signal of said selection circuit during said second period, so as to generate said level control signal in accordance with said detected level of said output signal of said selection circuit, said level control signal being supplied to said first input circuit.
Claim 8
Dependent Claim
66 words
A background noise generating apparatus claimed in claim wherein said level control circuit includes: a level control signal generating circuit for generating said level control signal in accordance with said output of said first input circuit; and a holding circuit for holding and outputting said level control signal generated in said level control signal generating circuit, during said first period in accordance with said second clock.
References Cited (Backward Citations)
US5121349A
Cited
US5570307A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |