Digital noise generator

Claim 2

A digital noise generator comprising: a pseudo-random bit sequence generator for generating and outputting a pseudo-random bit sequence; an amplitude control circuit for converting an amplitude control signal supplied from an external circuit to an amplitude code-word in accordance with a predetermined conversion rule; and a pulse code modulation (PCM) code-word-generating shift register which fetches the pseudo-random bit sequence and the amplitude code-word and generates and outputs a pseudo-random noise signal which conforms to a PCM coding rule.

Claim 3

A digital noise generator according to claim 1, wherein said amplitude control circuit comprises a nonvolatile memory for storing a code conversion table based on a rule of conversion from the amplitude control signal to the amplitude code-word, the amplitude control signal being converted to the amplitude code-word by reference to said code conversion table.

Claim 4

A digital noise generator according to claim 2, wherein said nonvolatile memory stores said code conversion table for converting the amplitude control signal to the PCM code-word based on the μ-law PCM coding rule.

Claim 5

A digital noise generator according to claim 2, wherein said nonvolatile memory stores said code conversion table for converting the amplitude control signal to the PCM code-word based on the A-law PCM coding rule stipulated in the CCITT recommendation G.711.

Claim 6

A digital noise generator according to claim 2, wherein said nonvolatile memory stores said code conversion table for converting the amplitude control signal to the PCM code-word based on a linear PCM coding rule.

Claim 7

A digital noise generator according to claim 1, wherein said amplitude control circuit outputs said amplitude code-word, and said pseudo-random bit sequence generator outputs the pseudo-random bit sequence in response to a PCM sampling clock signal of a predetermined period which is supplied from an external circuit, and said PCM code-word-generating shift register fetches the pseudo-random bit sequence and the amplitude code-word in response to the PCM sampling clock signal.

Claim 8

A digital noise generator according to claim 6, wherein the pseudo-random bit sequence is stored in the most significant bit position of said PCM code-word-generating shift register and the amplitude code-word is stored in the remaining bit positions.

Claim 9

A digital noise generator according to claim 7, wherein said PCM code-word-generating shift register serially outputs the stored content as the pseudo-random noise signal in response to a serial clock signal.

Claim 10

A digital noise generator according to claim 8, wherein said PCM code-word-generating shift register is an 8-bit shift register.

Claim 11

A digital noise generator according to claim 7, wherein said PCM code-word-generating shift register is an 8-bit shift register.

Claim 12

A digital noise generator according to claim 6, wherein said PCM code-word-generating shift register serially outputs the stored content as the pseudo-random noise signal in response to a serial clock signal.

Claim 13

A digital noise generator according to claim 11, wherein said PCM code-word-generating shift register is an 8-bit shift-register.

Claim 14

A digital noise generator according to claim 6, wherein said PCM code-word-generating shift register is an 8-bit shift register.

Claim 15

A digital noise generator according to claim 1, wherein said PCM code-word-generating shift register serially outputs the pseudo-random noise signal in response to a serial clock signal.

Claim 16

A digital noise generator according to claim 14, wherein said PCM code-word-generating shift register is an 8-bit shift register.

Claim 17

A digital noise generator comprising: a pseudo-random bit sequence generator which includes a shift register with a predetermined number of bits and an exclusive-OR circuit for fetching an output and intermediate output of said shift register so as to determine an exclusive-OR and effect a feedback input to said shift register and which is adapted to output an output of said shift register as a pseudo-random bit sequence; an amplitude control circuit for converting an amplitude control signal supplied from an external circuit to an amplitude code-word in accordance with a predetermined conversion rule; and a pulse code modulation (PCM) code-word-generating shift register which fetches the pseudo-random bit sequence and the amplitude code-word and generates and outputs a pseudo-random noise signal which conforms to a PCM coding rule.

Claim 18

A digital noise generator comprising: a pseudo-random bit sequence generator which includes a shift register with a predetermined number of bits and an exclusive-OR circuit for fetching an output and intermediate output of said shift register so as to determine an exclusive-OR and effect a feedback input to said shift register and which is adapted to output an output of said shift register as a pseudo-random bit sequence; an amplitude control circuit for converting an amplitude control signal supplied from an external circuit to an amplitude code-word in accordance with a predetermined conversion rule; and a pulse code modulation (PCM) code-word-generating shift register which fetches the pseudo-random bit sequence and the amplitude code-word and generates and outputs a pseudo-random noise signal which conforms to a PCM coding rule.

Claim 19

A digital noise generator according to claim 16, wherein said amplitude control circuit comprises a nonvolatile memory for storing a code conversion table based on a rule of conversion from the amplitude control signal to the amplitude code-word, the amplitude control signal being converted to the amplitude code-word by reference to said code conversion table.

Claim 20

A digital noise generator according to claim 17, wherein: said nonvolatile memory stores said code conversion table for converting the amplitude control signal to the amplitude code-word based on the μ-law PCM coding rule; said pseudo-random bit sequence generator outputs the pseudo-random bit sequence in response to a PCM sampling clock signal of a predetermined period which is supplied from an external circuit; said amplitude control circuit outputs the amplitude code-word in response to the PCM sampling clock signal; said PCM code-word-generating shift register fetches the pseudo-random bit sequence and the amplitude code-word in response to the PCM sampling clock signal; and the pseudo-random bit sequence is stored in the most significant bit position of said PCM code-word-generating shift register, said bit position indicating an output polarity, and the amplitude code-word is stored in the remaining bit positions.

Claim 21

A digital noise generator according to claim 18, wherein said PCM code-word-generating shift register serially outputs the pseudo-random noise signal in response to a serial clock signal.

Claim 22

A digital noise generator according to claim 19, wherein said PCM code-word-generating shift register is an 8-bit shift register.