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US5724060A Expired / Lapsed US ⏱️ 0.0 years remaining

Multiplex addressing of ferro-electric liquid crystal displays

Assignee: Qinetiq Ltd
•
Filing: 1994-01-26
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Granted: 1998-03-03
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Expires: 2014-01-26
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Abstract

Abstract The invention provides a ferro-electric liquid crystal display (FLCDs) with reduced voltages requirements for driver circuits. This enables standard drivers circuits designed to rms address twisted nematic type of displays, to be used for FLCDs. Displays are formed by cells containing smectic liquid crystal material. The cell walls are surface treated and carry e.g. row and column electrodes forming an x,y matrix of addressable display elements. The smectic liquid crystal material switches between two states upon application of a dc pulse of appropriate amplitude, polarity, and time. Addressing waveforms are strobe waveforms, e.g. two pulses of opposite polarity in successive time slots, applied to each row in turn. Data waveforms are, e.g. dc pulses of alternate polarity with each pulse lasting one time slot ts. Two data waveforms are needed to switch between the two states; one data waveform is the inverse of the other. Typically a strobe waveform pulse may be 50 volts. In the invention a voltage reduction waveform (VRW) is added to both strobe and data waveforms. This has the effect of reducing the maximum amplitude of voltage needed by the driver circuits, whilst leaving the resultant voltage appearing at a display element at the same value as if VRW were not used. With a reduced voltage requirement, driver circuits previously used for relatively low voltage menatic material type of displays can be used to switch smectic materials.

Inventors

  • 👤 Alistair Graham
  • 👤 Jonathan R. Hughes
  • 👤 Michael John Towler

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 02:43
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3696; G09G3/3622; G09G3/3629; G09G2310/00; G09G2310/02; G09G2310/0202; G09G2310/0205; G09G2310/06; G09G2310/061

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 186 words
A multiplex addressed liquid crystal display comprising: a liquid crystal cell including a layer of ferro-electric smectic liquid crystal material contained between two substrates, each substrate bearing a set of electrodes, said sets of electrodes arranged to form collectively a matrix of addressable display elements having addressable intersections; means, responsive to a data waveform, a strobe waveform and a voltage reduction waveform, for generating modified data and modified strobe waveforms of unipolar pulses in successive time slots (ts) for applying to the, two sets of electrodes, said generating means combining a data waveform and a voltage reduction waveform to form said modified data waveform and for applying said modified data waveform to one set of electrodes, and combining said strobe waveform and said voltage reduction waveform to form said modified strobe waveform and for applying said modified strobe waveform to the other set of electrodes in a multiplexed manner, means for controlling the order of data waveforms so that a desired display pattern is obtained wherein voltage levels applied to the generating means are reduced whilst maintaining the resultant voltage level appearing at the addressable intersections.
Claim 2
Dependent Claim 186 words
A multiplex addressed liquid crystal display comprising: a liquid crystal cell including a layer of ferro-electric smectic liquid crystal material contained between two substrates, each substrate bearing a set of electrodes, said sets of electrodes arranged to form collectively a matrix of addressable display elements having addressable intersections; means, responsive to a data waveform, a strobe waveform and a voltage reduction waveform, for generating modified data and modified strobe waveforms of unipolar pulses in successive time slots (ts) for applying to the, two sets of electrodes, said generating means combining a data waveform and a voltage reduction waveform to form said modified data waveform and for applying said modified data waveform to one set of electrodes, and combining said strobe waveform and said voltage reduction waveform to form said modified strobe waveform and for applying said modified strobe waveform to the other set of electrodes in a multiplexed manner, means for controlling the order of data waveforms so that a desired display pattern is obtained wherein voltage levels applied to the generating means are reduced whilst maintaining the resultant voltage level appearing at the addressable intersections.
Claim 3
Dependent Claim 104 words
The display of claim 1 wherein the generating means includes: row driver circuits having at least three different voltage level inputs, two control inputs (DATA-IN, & M), a serial-in parallel-out multistage shift register having a separate stage associated with each row electrode whereby a row waveform of at least three different voltage levels may be applied to each row electrode in sequence, column driver circuits having at least three different voltage level inputs, two control inputs (DATA-IN, & M), a serial-in parallel-out multistage shift register, and a latch associated with each stage output, whereby a column waveform may be applied to each column electrode.
Claim 4
Dependent Claim 25 words
The display of claim 1 wherein the generating means is arranged to address the display by strobe pulses of opposite polarity in successive field times.
Claim 5
Dependent Claim 29 words
The display of claim 2 wherein the generating means is arranged to address the display by a blanking waveform of one polarity and a strobe pulse of opposite polarity.
Claim 6
Dependent Claim 26 words
The display of claim 2 wherein the row driver circuits have four different voltage level inputs, and the column driver circuits have four different level inputs.
Claim 7
Dependent Claim 26 words
The display of claim 2 wherein the row driver circuits have three different voltage level inputs and the column driver circuits have three different level inputs.

References Cited (Backward Citations)

US5548303A Cited
US5381254A Cited
US4779956A Cited
US4795239A Cited
US5440412A Cited
US4893117A Cited
US5543945A Cited
US5363225A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-03-02 2001-09-01 2002-03-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-03-02 2005-09-01 2006-03-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-03-02 2009-09-01 2010-03-03 $7700.00 Window Closed / Lapsed

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