Patent US5721867A successfully refreshed from Google Patents.
US5721867A
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Method and apparatus for executing single beat write store instructions during a cache store linefill operation
Assignee: International Business Machines Corp
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Filing: 1996-04-01
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Granted: 1998-02-24
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Expires: 2016-04-01
Abstract
Abstract A method and apparatus for executing a single beat write (SBW) store instruction during a cache store linefill operation are disclosed. In accordance with the present disclosure, an address associated with the cache memory store linefill operation is first received. This address comprises a tag portion and an index portion. For the cache store linefill operation, the tag portion of this address is sent to a tag latch while the index portion is sent to a burst index latch. During the cache store linefill operation, a second address associated with the single beat write store instruction is received. This second address also comprises a tag portion and an index portion. In response to a determination that a critical word of the cache memory store linefill has been received, the tag portion of the second address is sent to the tag latch and the index portion of the second address is sent to an SBW index latch. By doing so, the single beat write store instruction may be executed before the completion of the cache store linefill operation.
Inventors
- 👤 Belliappa Manavattira Kuttanna
- 👤 Sung-Ho Park
- 👤 Rajesh Bhikhubhai Patel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:35
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
151 words
A method for executing a single beat write instruction during a cache memory operation, said method comprising the steps of: receiving a first address associated with said cache memory operation, wherein said first address comprises a tag portion and an index portion; writing said tag portion of said first address to a tag latch and writing said index portion of said first address to a first index latch; receiving a second address associated with said single beat write instruction, wherein said second address comprises a tag portion and an index portion; and in response to a determination that a critical word for said cache memory operation has been received, writing said tag portion of said second address to said tag latch and writing said index portion of said second address to a second index latch, wherein said single beat write instruction is executable before the completion of said cache memory operation.
Claim 2
Independent Claim
151 words
A method for executing a single beat write instruction during a cache memory operation, said method comprising the steps of: receiving a first address associated with said cache memory operation, wherein said first address comprises a tag portion and an index portion; writing said tag portion of said first address to a tag latch and writing said index portion of said first address to a first index latch; receiving a second address associated with said single beat write instruction, wherein said second address comprises a tag portion and an index portion; and in response to a determination that a critical word for said cache memory operation has been received, writing said tag portion of said second address to said tag latch and writing said index portion of said second address to a second index latch, wherein said single beat write instruction is executable before the completion of said cache memory operation.
Claim 3
Dependent Claim
34 words
The method for executing a single beat write instruction during a cache memory operation according to claim 1, wherein said method further comprises the step of sending a request for said cache memory operation.
Claim 4
Dependent Claim
35 words
The method for executing a single beat write instruction during a cache memory operation according to claim 1, wherein said method further comprises the step of sending a request for said single beat write instruction.
Claim 5
Dependent Claim
34 words
The method for executing a single beat write instruction during a cache memory operation according to claim 1, wherein said method further comprises the step of returning to said receiving a second address step.
Claim 6
Dependent Claim
140 words
A processor for executing a single beat write instruction during a cache memory operation, said processor comprising: means for receiving a first address associated with said cache memory operation, wherein said first address comprises a tag portion and an index portion; means for writing said tag portion of said first address to a tag latch and writing said index portion of said first address to a first index latch; means for receiving a second address associated with said single beat write instruction, wherein said second address comprises a tag portion and an index portion; and means for writing said tag portion of said second address to said tag latch and writing said index portion of said second address to a second index latch, in response to a determination that a critical word of said cache memory operation has been received.
Claim 7
Dependent Claim
140 words
A processor for executing a single beat write instruction during a cache memory operation, said processor comprising: means for receiving a first address associated with said cache memory operation, wherein said first address comprises a tag portion and an index portion; means for writing said tag portion of said first address to a tag latch and writing said index portion of said first address to a first index latch; means for receiving a second address associated with said single beat write instruction, wherein said second address comprises a tag portion and an index portion; and means for writing said tag portion of said second address to said tag latch and writing said index portion of said second address to a second index latch, in response to a determination that a critical word of said cache memory operation has been received.
Claim 8
Dependent Claim
29 words
The processor for executing a single beat write instruction during a cache memory operation according to claim 5, wherein said cache memory operation is a burst store linefill operation.
Claim 9
Dependent Claim
34 words
The processor for executing a single beat write instruction during a cache memory operation according to claim 5, wherein said processor further comprises the means for writing a request for said cache memory operation.
Claim 10
Dependent Claim
35 words
The processor for executing a single beat write instruction during a cache memory operation according to claim 5, wherein said processor further comprises the means for writing a request for said single beat write instruction.
Claim 11
Independent Claim
114 words
An apparatus for executing a single beat write instruction during a cache memory operation, said apparatus comprising: a tag latch for receiving a tag portion of a first address associated with said cache memory operation and a tag portion of a second address associated with said single beat write instruction; a first index latch for receiving an index portion of said first address associated with said cache memory operation, said first index latch is connected in parallel with said tag latch; and a second index latch for receiving an index portion of said second address associated with said cache memory operation, said second index latch is connected in parallel with said first index latch.
Claim 12
Independent Claim
114 words
An apparatus for executing a single beat write instruction during a cache memory operation, said apparatus comprising: a tag latch for receiving a tag portion of a first address associated with said cache memory operation and a tag portion of a second address associated with said single beat write instruction; a first index latch for receiving an index portion of said first address associated with said cache memory operation, said first index latch is connected in parallel with said tag latch; and a second index latch for receiving an index portion of said second address associated with said cache memory operation, said second index latch is connected in parallel with said first index latch.
Claim 13
Dependent Claim
28 words
The apparatus for executing single beat write instructions during a cache memory operation according to claim 9, wherein said cache memory operation is a burst store linefill operation.
Claim 14
Dependent Claim
38 words
The apparatus for executing single beat write instructions during a cache memory operation according to claim 9, wherein an output of said first index latch and an output of said second index latch are connected to a multiplexer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-23 | 2001-08-25 | 2002-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-23 | 2005-08-25 | 2006-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-23 | 2009-08-25 | 2010-02-24 | $7700.00 | Window Closed / Lapsed |