Patent US3775222A successfully refreshed from Google Patents.
Patent US5715425A successfully refreshed from Google Patents.
US5715425A
Expired / Lapsed
US
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Apparatus and method for prefetching data into an external cache
Assignee: Oracle America Inc
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Filing: 1996-02-22
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Granted: 1998-02-03
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Expires: 2016-02-22
Abstract
Abstract A central processing unit is connected to an external memory including system memory and an external cache. The central processing unit includes a First-In-First-Out (FIFO) load buffer configured to generate an access to the external memory in response to a data prefetch command. The access to external memory has an associated data load latency period as data is moved from the system memory into the external cache. Instead of requiring the access to external memory to be completed before another FIFO load buffer address is processed, as is typically required in a FIFO load buffer configuration, the FIFO load buffer responds to the data prefetch command by processing additional stored addresses during the data load latency period.
Inventors
- 👤 Gary S. Goldman
- 👤 Bruce E. Petrick
- 👤 Marc Tremblay
- 👤 Dale R. Greenley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:48
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F12/0844; G06F12/0855; G06F12/0859; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/383; G06F2212/00; G06F2212/60; G06F2212/6028
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
146 words
A computer, comprising: (I) an external memory; and (II) a central processing unit, connected to said external memory, said central processing unit including (A) an instruction processing unit to process instructions including a prefetch command, (B) an internal cache to selectively generate an internal cache miss signal in response to an address signal received from said instruction processing unit, and (C) a First-In-First-Out (FIFO) load buffer connected to said instruction processing unit, said FIFO load buffer configured to generate (i) a first access to said external memory in response to said data prefetch command, said first access having an associated data load latency period, and (ii) a second access to said external memory, during said data load latency period, in response to said internal cache miss signal such that said first access to said external memory does not stall said second access to said external memory.
Claim 2
Dependent Claim
146 words
A computer, comprising: (I) an external memory; and (II) a central processing unit, connected to said external memory, said central processing unit including (A) an instruction processing unit to process instructions including a prefetch command, (B) an internal cache to selectively generate an internal cache miss signal in response to an address signal received from said instruction processing unit, and (C) a First-In-First-Out (FIFO) load buffer connected to said instruction processing unit, said FIFO load buffer configured to generate (i) a first access to said external memory in response to said data prefetch command, said first access having an associated data load latency period, and (ii) a second access to said external memory, during said data load latency period, in response to said internal cache miss signal such that said first access to said external memory does not stall said second access to said external memory.
Claim 3
Dependent Claim
32 words
The apparatus of claim 1 wherein said external memory includes system memory and an external cache, said system memory loading pre-load data into said external cache during said data load latency period.
Claim 4
Dependent Claim
37 words
The apparatus of claim 2 wherein said FIFO load buffer is configured to initiate a transfer of said pre-load data from said external cache to an execution unit in response to a subsequent internal cache miss signal.
Claim 5
Dependent Claim
15 words
The apparatus of claim 3 wherein said execution unit includes a floating point processing unit.
Claim 6
Independent Claim
32 words
The apparatus of claim i wherein said First-In-First-Out (FIFO) load buffer is configured to generate a second read and a third read to said external memory, during said data load latency period.
Claim 7
Dependent Claim
33 words
The apparatus of claim 1 wherein said FIFO load buffer is configured to respond to said internal cache miss signal by loading cache miss data from said external memory into said internal cache.
Claim 8
Dependent Claim
34 words
The apparatus of claim 6 wherein said FIFO load buffer is configured to wait for said cache miss data to be loaded from said external memory into said internal cache before processing another address.
Claim 9
Dependent Claim
106 words
A computer, comprising: an external memory; and a central processing unit connected to said external memory, said central processing unit including an instruction processing unit to generate a load address command and a data prefetch command; a load/store unit connected to said instruction processing unit, said load/store unit including an internal cache to process said load address command and generate an internal cache miss signal, and a First-In-First-Out (FIFO) load buffer to receive said internal cache miss signal and said data prefetch command, said FIFO load buffer processing said internal cache miss signal during an access to said external memory caused by said data prefetch command.
Claim 10
Dependent Claim
106 words
A computer, comprising: an external memory; and a central processing unit connected to said external memory, said central processing unit including an instruction processing unit to generate a load address command and a data prefetch command; a load/store unit connected to said instruction processing unit, said load/store unit including an internal cache to process said load address command and generate an internal cache miss signal, and a First-In-First-Out (FIFO) load buffer to receive said internal cache miss signal and said data prefetch command, said FIFO load buffer processing said internal cache miss signal during an access to said external memory caused by said data prefetch command.
Claim 11
Dependent Claim
32 words
The apparatus of claim 8 wherein said FIFO load buffer is configured to generate a plurality of memory reads during said access to said external memory caused by said data prefetch command.
Claim 12
Dependent Claim
55 words
The apparatus of claim 8 wherein said FIFO load buffer is configured to respond to said internal cache miss signal by loading cache miss data from said external memory into said internal cache, and wait for said cache miss data to be loaded from said external memory into said internal cache before processing another address.
Claim 13
Independent Claim
92 words
A method of operating a computer, said method comprising the steps of: routing a data prefetch command to a First-In-First-Out(FIFO) load buffer; accessing an external cache with said FIFO load buffer in response to said data prefetch command; loading data from system memory into said external cache in response to said accessing step; retiring the position of said data prefetch command in said FIFO load buffer before said loading step is completed; and reading said external cache with a new address in said FIFO load buffer before said loading step is completed.
Claim 14
Independent Claim
92 words
A method of operating a computer, said method comprising the steps of: routing a data prefetch command to a First-In-First-Out(FIFO) load buffer; accessing an external cache with said FIFO load buffer in response to said data prefetch command; loading data from system memory into said external cache in response to said accessing step; retiring the position of said data prefetch command in said FIFO load buffer before said loading step is completed; and reading said external cache with a new address in said FIFO load buffer before said loading step is completed.
Claim 15
Dependent Claim
78 words
The method of claim 11 further comprising the steps of: generating an internal cache miss signal with an internal cache in response to a load address command; passing said internal cache miss signal to said FIFO load buffer; and re-accessing, before said loading step is completed, said external cache with said FIFO load buffer in response to said internal cache miss signal, said re-accessing step causing a transfer of data from said external cache into said internal cache.
Claim 16
Dependent Claim
39 words
The method of claim 12 further comprising the step of retiring the position of said internal cache miss signal in said FIFO load buffer after said transfer of data from said external cache into said internal cache is completed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-02 | 2001-08-04 | 2002-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-02 | 2005-08-04 | 2006-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-02 | 2009-08-04 | 2010-02-03 | $7700.00 | Window Closed / Lapsed |