US5715209A
Expired / Lapsed
US
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Integrated circuit memory devices including a dual transistor column selection switch and related methods
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-05-10
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Granted: 1998-02-03
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Expires: 2016-05-10
Abstract
Abstract An integrated circuit memory device includes a plurality of memory units arranged in an array of columns and banks. Each of the memory units includes a memory cell, and a bit line coupled to the memory cell wherein the bit line receives a bit of information from the memory cell. Each of a plurality of global column selection lines extends along a respective column of the memory units through each of the banks. A column decoder generates global column selection signals on the plurality of global column selection lines. Each of a plurality of input/output lines extends along a respective bank of the memory units. In addition, each of a plurality of memory unit selection circuits connects a respective bit line of a respective memory unit to a respective input/output line in response to a global column selection signal on the respective global column selection line and a bank selection column address signal. Accordingly, only one bit line from the plurality of memory units is connected to a respective one of the input/output lines at a time.
Inventors
- 👤 Jei-Hwan Yoo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:57
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C8/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
302 words
An integrated circuit memory device comprising: a plurality of memory units arranged in an array of columns and banks, wherein each of said memory units includes, at least one memory cell, and a bit line coupled to said at least one memory cell, wherein said bit line receives a bit of information from said at least one memory cell; a plurality of global column selection lines each of which extends along a respective column of said memory units through each of said banks; a column decoder which generates global column selection signals on said plurality of global column selection lines; a plurality of input/output lines each of which extends along a respective bank of said memory units; and a plurality of memory unit selection circuits, each of which connects a respective bit line of a respective memory unit to a respective input/output line responsive to a respective global column selection signal on said respective global column selection line and a bank select column address signal so that only one bit line from said plurality of memory units is connected to a respective one of said input/output lines at a time; wherein each of said memory selection circuits further comprises a column selection transistor which connects said respective bit line to said respective input/output line responsive to the respective global column selection signal and the bank select column address signal and wherein each of said memory selection circuits further comprises, a first bank selection transistor which electrically connects a gate of said column selection transistor to said respective global column selection line responsive to the bank select column address signal and a second bank selection transistor which electrically connects said gate of said column selection transistor to a predetermined disable signal responsive to a logical inverse of said bank select column address signal.
Claim 2
Dependent Claim
302 words
An integrated circuit memory device comprising: a plurality of memory units arranged in an array of columns and banks, wherein each of said memory units includes, at least one memory cell, and a bit line coupled to said at least one memory cell, wherein said bit line receives a bit of information from said at least one memory cell; a plurality of global column selection lines each of which extends along a respective column of said memory units through each of said banks; a column decoder which generates global column selection signals on said plurality of global column selection lines; a plurality of input/output lines each of which extends along a respective bank of said memory units; and a plurality of memory unit selection circuits, each of which connects a respective bit line of a respective memory unit to a respective input/output line responsive to a respective global column selection signal on said respective global column selection line and a bank select column address signal so that only one bit line from said plurality of memory units is connected to a respective one of said input/output lines at a time; wherein each of said memory selection circuits further comprises a column selection transistor which connects said respective bit line to said respective input/output line responsive to the respective global column selection signal and the bank select column address signal and wherein each of said memory selection circuits further comprises, a first bank selection transistor which electrically connects a gate of said column selection transistor to said respective global column selection line responsive to the bank select column address signal and a second bank selection transistor which electrically connects said gate of said column selection transistor to a predetermined disable signal responsive to a logical inverse of said bank select column address signal.
Claim 3
Dependent Claim
95 words
An integrated circuit memory device according to claim 1 wherein each of said memory units further includes a complementary bit line coupled to said memory cell which receives a complementary bit of information from said memory cell, said integrated circuit memory device further comprising a plurality of complementary input/output lines, each of which extends along a respective bank of said memory units, and wherein said respective memory selection circuit connects said respective complementary bit line to said respective complementary input/output line responsive to the global column selection signal and the bank select column address signal.
Claim 4
Independent Claim
235 words
A method for selecting a memory unit of an integrated circuit memory device including a plurality of memory units arranged in an array of columns and banks, and a plurality of input/output lines wherein each of said input/output lines extends along a respective bank of said memory units, wherein each of said memory units includes at least one memory cell, a bit line coupled to said at least one memory cell, and a column selection transistor connected between the bit line and the respective input/output line, said method comprising the steps of: generating a global column selection signal for each column of said memory units; generating a bank select column address signal for each bank of said memory units; and connecting a bit line of a respective memory unit to the respective input/output line through said column selection transistor responsive to a respective global column selection signal and a respective bank select column address signal so that only one bit line from said plurality of memory units is connected to a respective one of said input/output lines at a time; wherein said connecting step further comprises the steps of, connecting a gate of said column selection transistor to said respective column selection signal responsive to the bank select signal; and connecting said gate of said column selection transistor to a predetermined disable signal responsive to a logical inverse of said bank select column address signal.
Claim 5
Independent Claim
235 words
A method for selecting a memory unit of an integrated circuit memory device including a plurality of memory units arranged in an array of columns and banks, and a plurality of input/output lines wherein each of said input/output lines extends along a respective bank of said memory units, wherein each of said memory units includes at least one memory cell, a bit line coupled to said at least one memory cell, and a column selection transistor connected between the bit line and the respective input/output line, said method comprising the steps of: generating a global column selection signal for each column of said memory units; generating a bank select column address signal for each bank of said memory units; and connecting a bit line of a respective memory unit to the respective input/output line through said column selection transistor responsive to a respective global column selection signal and a respective bank select column address signal so that only one bit line from said plurality of memory units is connected to a respective one of said input/output lines at a time; wherein said connecting step further comprises the steps of, connecting a gate of said column selection transistor to said respective column selection signal responsive to the bank select signal; and connecting said gate of said column selection transistor to a predetermined disable signal responsive to a logical inverse of said bank select column address signal.
Claim 6
Dependent Claim
261 words
An integrated circuit memory device comprising: a plurality of memory units arranged in an array of columns and banks, wherein each of said memory units includes, at least one memory cell, and a bit line coupled to said at least one memory cell, wherein said bit line receives a bit of information from said at least one memory cell; a plurality of global column selection lines each of which extends along a respective column of said memory units through each of said banks; a column decoder which generates global column selection signals on said plurality of global column selection lines; a plurality of input/output lines each of which extends along a respective bank of said memory units; a plurality of column selection circuits each of which generates a local column selection signal for a respective bit line of a respective memory unit responsive to a bank select column address signal and the global column selection signal on said global column selection line adjacent said respective memory unit; and a plurality of column selection transistors each of which connects said respective bit line to a respective input/output line responsive to the local column selection signal; wherein each of said column selection circuits comprises: a first transistor which electrically connects a gate of said column selection transistor to said respective global column selection line responsive to the bank select column address signal; and a second transistor which electrically connects said gate of said column selection transistor to a predetermined disable signal responsive to a logical inverse of said bank select column address signal.
Claim 7
Dependent Claim
261 words
An integrated circuit memory device comprising: a plurality of memory units arranged in an array of columns and banks, wherein each of said memory units includes, at least one memory cell, and a bit line coupled to said at least one memory cell, wherein said bit line receives a bit of information from said at least one memory cell; a plurality of global column selection lines each of which extends along a respective column of said memory units through each of said banks; a column decoder which generates global column selection signals on said plurality of global column selection lines; a plurality of input/output lines each of which extends along a respective bank of said memory units; a plurality of column selection circuits each of which generates a local column selection signal for a respective bit line of a respective memory unit responsive to a bank select column address signal and the global column selection signal on said global column selection line adjacent said respective memory unit; and a plurality of column selection transistors each of which connects said respective bit line to a respective input/output line responsive to the local column selection signal; wherein each of said column selection circuits comprises: a first transistor which electrically connects a gate of said column selection transistor to said respective global column selection line responsive to the bank select column address signal; and a second transistor which electrically connects said gate of said column selection transistor to a predetermined disable signal responsive to a logical inverse of said bank select column address signal.
Claim 8
Dependent Claim
103 words
An integrated circuit memory device according to claim 4 wherein each of said memory units further includes a complementary bit line coupled to said at least one memory cell which receives a complementary bit of information from said at least one memory cell, said integrated circuit memory device further comprising: a plurality of complementary input/output lines each of which extends along a respective bank of said memory units; and a plurality of complementary column selection transistors each of which connects said respective complementary bit line of said respective memory unit to said respective complementary input/output line responsive to the local column selection signal.
Claim 9
Dependent Claim
265 words
A semiconductor memory device comprising: a plurality of memory cells arranged in an array of columns and banks; a plurality of bit line pairs wherein each of said pairs of bit lines is coupled to a respective memory cell; a plurality of column select transistor pairs each of which is connected to a respective pair of bit lines, each of said column select transistors including an input gate and first and second input/output electrodes and each of said first input/output electrodes being connected to a respective bit line; a plurality of global column select lines each of which extends along a respective column of said memory cells through each of said banks; a column decoder for providing global column select signals along said plurality of global column select lines; a plurality of local column select lines each of which is connected to respective input gates of a respective column select transistor pair; and a plurality of connecting means for connecting each of said global column select lines with respective local column select lines in response to a bank selection signal; wherein each of said connecting means respectively includes a first MOS transistor with first and second input/output electrodes respectively connected to a respective global column select line and a respective local column select line and with a gate input for receiving said bank selection signal and a second MOS transistor with first and second input/output electrodes respectively connected to a predetermined disable signal and said respective local column select line and with a gate input for receiving a logical inverse of said bank selection signal.
Claim 10
Dependent Claim
265 words
A semiconductor memory device comprising: a plurality of memory cells arranged in an array of columns and banks; a plurality of bit line pairs wherein each of said pairs of bit lines is coupled to a respective memory cell; a plurality of column select transistor pairs each of which is connected to a respective pair of bit lines, each of said column select transistors including an input gate and first and second input/output electrodes and each of said first input/output electrodes being connected to a respective bit line; a plurality of global column select lines each of which extends along a respective column of said memory cells through each of said banks; a column decoder for providing global column select signals along said plurality of global column select lines; a plurality of local column select lines each of which is connected to respective input gates of a respective column select transistor pair; and a plurality of connecting means for connecting each of said global column select lines with respective local column select lines in response to a bank selection signal; wherein each of said connecting means respectively includes a first MOS transistor with first and second input/output electrodes respectively connected to a respective global column select line and a respective local column select line and with a gate input for receiving said bank selection signal and a second MOS transistor with first and second input/output electrodes respectively connected to a predetermined disable signal and said respective local column select line and with a gate input for receiving a logical inverse of said bank selection signal.
Claim 11
Dependent Claim
18 words
A semiconductor memory device according to claim 6 wherein said bank selection signal is a column address signal.
Claim 12
Dependent Claim
18 words
A semiconductor memory device according to claim 6 wherein said bank selection signal is a column address signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-02 | 2001-08-04 | 2002-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-02 | 2005-08-04 | 2006-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-02 | 2009-08-04 | 2010-02-03 | $7700.00 | Window Closed / Lapsed |