Patent US5715200A successfully refreshed from Google Patents.
US5715200A
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US
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Memory devices
Assignee: Accelerix Ltd
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Filing: 1995-11-29
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Granted: 1998-02-03
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Expires: 2015-11-29
Abstract
Abstract A memory device with a dynamic random access memory (DRAM) having an array of a plurality of rows and columns of memory elements; a cache memory formed integrally with the DRAM and includinmg at least one register with a plurality of memory elements and connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in the at least one register, n being an integer greater than or equal to 2; and a connector for connecting the at least one register to the DRAM, the connector for the at least one register being a bus having a width corresponding to the number of memory elements therein.
Inventors
- 👤 Dennis A. Fielder
- 👤 James H. Derbyshire
- 👤 Peter B. Gillingham
- 👤 Cormac M. O'Connell
- 👤 Randall R. Torrance
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:03
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
124 words
A memory device, comprising: a dynamic random access memory (DRAM) comprising an array of a plurality of rows and columns of memory elements; cache memory means formed integrally with the DRAM and comprising at least one register comprising a plurality of memory elements and being connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in said at least one register, n being an integer greater than or equal to 2; and connecting means connecting said at least one register to the DRAM, the connecting means for said at least one register being a bus means having a width corresponding to the number of memory elements therein.
Claim 2
Dependent Claim
124 words
A memory device, comprising: a dynamic random access memory (DRAM) comprising an array of a plurality of rows and columns of memory elements; cache memory means formed integrally with the DRAM and comprising at least one register comprising a plurality of memory elements and being connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in said at least one register, n being an integer greater than or equal to 2; and connecting means connecting said at least one register to the DRAM, the connecting means for said at least one register being a bus means having a width corresponding to the number of memory elements therein.
Claim 3
Dependent Claim
39 words
A memory device according to claim 1 in which said at least one register has a number of memory elements which is one half or one third of the number of memory elements in a row of the DRAM.
Claim 4
Dependent Claim
16 words
A memory device according to claim 2 in which the cache memory comprises three said registers.
Claim 5
Dependent Claim
30 words
A memory device according to claim 1, further comprising operation means formed integrally with the DRAM and cache memory means and performing operations on data held in the cache memory.
Claim 6
Dependent Claim
30 words
A memory device according to claim 2, further comprising operation means formed integrally with the DRAM and cache memory means and performing operations on data held in the cache memory.
Claim 7
Dependent Claim
30 words
A memory device according to claim 3, further comprising operation means formed integrally with the DRAM and cache memory means and performing operations on data held in the cache memory.
Claim 8
Dependent Claim
30 words
A memory device according to claim 5, further comprising operation means formed integrally with the DRAM and cache memory means and performing operations on data held in the cache memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-02 | 2001-08-04 | 2002-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-02 | 2005-08-04 | 2006-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-02 | 2009-08-04 | 2010-02-03 | $7700.00 | Window Closed / Lapsed |