Video signal compression apparatus for horizontal compression of a video signal

Claim 1

A video signal compression apparatus for compressing a video signal comprising: memory means for storing an input video signal and for outputting data value D n for address A n and data value D n+1 for address A n+1 when a read address A n is given; first counter means for outputting a reset signal responsive to a horizontal sync signal for reading by a system clock pulses; second counter means for counting said system clock pulses responsive to said reset signal from said first counter means to provide a counter output value; further memory means for outputting one of a plurality of previously stored values corresponding to said counter output value; first signal selector means for selecting one of the output of said further memory means and a fixed value to generate a first selector output value; first adder means for adding the first selector output value and the register value to generate a first adder output value; second signal selector means for selecting a read start address command responsive to said reset signal and for otherwise selecting said first adder output value to generate a second selector output value; register means for latching said second selector output value to generate a register output value, wherein an integer part of the register output value is said read address A n of said memory means; subtracter means for subtracting data D n from data D n+1 and generating a subtraction value; multiplier means for multiplying said subtraction value by a decimal part of said register output value to generate a multiplier output value; and second adder means for adding the data D n and the multiplier output value and for outputting said compressed video signal.