US5712178A
Expired / Lapsed
US
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Non-volatile semiconductor memory device and method for manufacturing the same
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-06-07
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Granted: 1998-01-27
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Expires: 2015-06-07
Abstract
Abstract An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.
Inventors
- 👤 Myoung-kwan Cho
- 👤 Jeong-Hyuk Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:44
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/30; H10B41/35; H10B41/41; H10B41/42; H10B41/49
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
168 words
A method for manufacturing a semiconductor memory device comprising the steps of: providing a semiconductor substrate of a first conductivity type defined into a cell array region and a peripheral circuit region; forming a second impurity-doped region of a second conductivity type in a surface portion of said semiconductor substrate in said cell array region; forming a first impurity-doped region of said first conductivity type enclosed by said second impurity-doped region; forming a memory device on said first impurity-doped region; forming a third impurity-doped region of said first conductivity type in a first surface portion of said semiconductor substrate in said peripheral circuit region; forming a fourth impurity-doped region of said second conductivity type in a third surface portion of said semiconductor substrate in said peripheral circuit region; forming a first MOS transistor on said third impurity-doped region, forming a second MOS transistor on a second surface portion of said semiconductor substrate in said peripheral circuit region; and forming a third MOS transistor on said fourth impurity-doped region.
Claim 2
Independent Claim
168 words
A method for manufacturing a semiconductor memory device comprising the steps of: providing a semiconductor substrate of a first conductivity type defined into a cell array region and a peripheral circuit region; forming a second impurity-doped region of a second conductivity type in a surface portion of said semiconductor substrate in said cell array region; forming a first impurity-doped region of said first conductivity type enclosed by said second impurity-doped region; forming a memory device on said first impurity-doped region; forming a third impurity-doped region of said first conductivity type in a first surface portion of said semiconductor substrate in said peripheral circuit region; forming a fourth impurity-doped region of said second conductivity type in a third surface portion of said semiconductor substrate in said peripheral circuit region; forming a first MOS transistor on said third impurity-doped region, forming a second MOS transistor on a second surface portion of said semiconductor substrate in said peripheral circuit region; and forming a third MOS transistor on said fourth impurity-doped region.
Claim 3
Dependent Claim
107 words
The method for manufacturing a semiconductor memory device as claimed in claim 1, where said memory device forming step further comprises the steps of: forming a first conductive layer pattern on said first impurity-doped region; forming an insulating layer pattern covering said first conductive layer pattern; forming a second conductive layer pattern on said insulating pattern; patterning said second conductive layer pattern, said insulating layer pattern and said first conductive layer pattern sequentially, to thereby form a control gate electrode and a floating gate electrode; implanting an impurity into said first impurity-doped region to thereby form a source region and a drain region of said memory device.
Claim 4
Dependent Claim
103 words
The method for manufacturing a semiconductor memory device as claimed in claim 1, wherein said second and fourth impurity-doped regions are formed by a method comprising the steps of: forming a first oxide layer on said semiconductor substrate; forming an anti-oxidative layer on said first oxide layer; forming a photoresist pattern on said anti-oxidative layer which exposes portions of said anti-oxidative layer where said second and fourth impurity-doped regions are to be formed; etching said exposed portions of said anti-oxidative layers; and implanting a second conductivity type impurity into surface portions of said semiconductor substrate via the etched portion of said anti-oxidative layer.
Claim 5
Dependent Claim
104 words
The method for manufacturing a semiconductor memory device as claimed in claim 1, wherein said first and third impurity-doped regions are formed by a method comprising the steps of: forming a first oxide layer and an anti-oxidative layer on said semiconductor substrate, excluding portions where said second impurity-doped region is formed; forming a second oxide layer on said second impurity-doped region; forming a photoresist pattern exposing a portion of said second oxide layer where said first impurity-doped region is to be formed and a portion of said anti-oxidative layer is to be formed; and implanting a first conductivity type impurity into said semiconductor substrate.
Claim 6
Dependent Claim
68 words
The method for manufacturing a semiconductor memory device as claimed in claim 4, wherein said first conductivity type impurity is firstly implanted at a first acceleration energy such that said first conductivity type impurity penetrates said second oxide layer and said anti-oxidative layer, and secondly implanted at a second acceleration energy such that said first conductivity type impurity penetrates said anti-oxidative layer but not said second oxide layer.
Claim 7
Dependent Claim
52 words
The method for manufacturing a semiconductor memory device as claimed in claim 4, said method further comprising the step of: etching said second oxide layer using said photoresist pattern as an etching mask to thereby expose a surface portion of said semiconductor substrate where said first impurity-doped region is to be formed.
Claim 8
Dependent Claim
59 words
The method for manufacturing a semiconductor memory device as claimed in claim 6, wherein said first conductivity type impurity is firstly implanted at a first acceleration energy such that said first conductivity type impurity does not penetrate said anti-oxidative layer, and secondly implanted at a second acceleration energy such that said first conductivity type impurity penetrates said anti-oxidative layer.
Claim 9
Dependent Claim
105 words
The method for manufacturing a semiconductor memory device as claimed in claim 4, said method further comprising the steps of: firstly implanting said first conductivity type impurity at a first acceleration energy such that said first conductivity type impurity penetrates said anti-oxidative layer but not said second oxide layer: etching said second oxide layer using said photoresist pattern as an etching mask to thereby expose a surface portion of said semiconductor substrate where said first impurity-doped region is to be formed; and secondly implanting said first conductivity type impurity at a second acceleration energy such that said first conductivity type impurity penetrates said anti-oxidative layer.
Claim 10
Dependent Claim
75 words
The method for manufacturing a semiconductor memory device as claimed in claim 1, wherein said first and third impurity-doped regions are formed by a method comprising the steps of: forming a first oxide layer on the whole surface of said semiconductor substrate; forming a photoresist pattern exposing portions of said first oxide layer where said first and third impurity-doped regions are to be formed; and implanting a first conductivity type impurity into said semiconductor substrate.
Claim 11
Independent Claim
222 words
A method for manufacturing a semiconductor memory device comprising the steps of: providing a P-type semiconductor substrate defined into a cell array region and a peripheral circuit region; forming a first N-well in a surface portion of said semiconductor substrate in said cell array region and a second N-well in a first surface of said semiconductor substrate in said peripheral circuit region; forming a first oxide layer and an anti-oxidative layer on a portion of said semiconductor substrate, excluding the portions where said first and second N-wells are formed; forming a second oxide layer which is thicker than said first oxide layer on said first and second N-wells; forming a photoresist pattern on said anti-oxidative layer and on said second oxide layer, said photoresist pattern exposing a portion of said anti-oxidative layer and a portion of said second oxide layer; implanting a P-type impurity into said semiconductor substrate; activating the implanted impurity to thereby form a first P-well enclosed by said first N-well and a second P-well in a third surface portion of said semiconductor substrate; forming an EEPROM memory cell on said first P-well; forming a first NMOS transistor on said second P-well; forming a second NMOS transistor on a second surface portion of said semiconductor substrate in said peripheral circuit region; and forming a PMOS transistor on said second N-well.
Claim 12
Independent Claim
222 words
A method for manufacturing a semiconductor memory device comprising the steps of: providing a P-type semiconductor substrate defined into a cell array region and a peripheral circuit region; forming a first N-well in a surface portion of said semiconductor substrate in said cell array region and a second N-well in a first surface of said semiconductor substrate in said peripheral circuit region; forming a first oxide layer and an anti-oxidative layer on a portion of said semiconductor substrate, excluding the portions where said first and second N-wells are formed; forming a second oxide layer which is thicker than said first oxide layer on said first and second N-wells; forming a photoresist pattern on said anti-oxidative layer and on said second oxide layer, said photoresist pattern exposing a portion of said anti-oxidative layer and a portion of said second oxide layer; implanting a P-type impurity into said semiconductor substrate; activating the implanted impurity to thereby form a first P-well enclosed by said first N-well and a second P-well in a third surface portion of said semiconductor substrate; forming an EEPROM memory cell on said first P-well; forming a first NMOS transistor on said second P-well; forming a second NMOS transistor on a second surface portion of said semiconductor substrate in said peripheral circuit region; and forming a PMOS transistor on said second N-well.
Claim 13
Independent Claim
161 words
A method for manufacturing a semiconductor memory device comprising the steps of: providing a semiconductor substrate of a first conductivity type defined into a cell array region and a peripheral circuit region; forming a second impurity-doped region of a second conductivity type in a surface portion of said semiconductor substrate in said cell array region; forming a first impurity-doped region of said first conductivity type enclosed by said second impurity-doped region; and forming a memory device on said first impurity-doped region having a first conductive layer pattern on said first impurity-doped region, an insulating layer pattern covering said first conductive layer pattern, a second conductive layer pattern on said insulating pattern, a control gate electrode and a floating gate electrode formed by patterning said second conductive layer pattern, said insulating layer pattern and said first conductive layer pattern sequentially, and a source region and a drain region of said memory device formed by implanting an impurity into said first impurity-doped region.
Claim 14
Independent Claim
161 words
A method for manufacturing a semiconductor memory device comprising the steps of: providing a semiconductor substrate of a first conductivity type defined into a cell array region and a peripheral circuit region; forming a second impurity-doped region of a second conductivity type in a surface portion of said semiconductor substrate in said cell array region; forming a first impurity-doped region of said first conductivity type enclosed by said second impurity-doped region; and forming a memory device on said first impurity-doped region having a first conductive layer pattern on said first impurity-doped region, an insulating layer pattern covering said first conductive layer pattern, a second conductive layer pattern on said insulating pattern, a control gate electrode and a floating gate electrode formed by patterning said second conductive layer pattern, said insulating layer pattern and said first conductive layer pattern sequentially, and a source region and a drain region of said memory device formed by implanting an impurity into said first impurity-doped region.
Claim 15
Dependent Claim
68 words
The method for manufacturing a semiconductor memory device as claimed in claim 11, said method further comprising the steps of: forming a third impurity-doped region of said first conductivity type in a first surface portion of said semiconductor substrate in said peripheral circuit region; and forming a fourth impurity-doped region of said second conductivity type in a third surface portion of said semiconductor substrate in said peripheral circuit.
Claim 16
Dependent Claim
60 words
The method for manufacturing a semiconductor memory device as claimed in claim 12, said method further comprising the steps of: forming a first MOS transistor on said third impurity-doped region; forming a second MOS transistor on a second surface portion of said semiconductor substrate in said peripheral circuit region; and forming a third MOS transistor on said fourth impurity-doped region.
Claim 17
Dependent Claim
103 words
The method for manufacturing a semiconductor memory device as claimed in claim 12, wherein said second and fourth impurity-doped regions are formed by a method comprising the steps of: forming a first oxide layer on said semiconductor substrate; forming an anti-oxidative layer on said first oxide layer; forming a photoresist pattern on said anti-oxidative layer which exposes portions of said anti-oxidative layer where said second and fourth impurity-doped regions are to be formed; etching said exposed portions of said anti-oxidative layers; and implanting a second conductivity type impurity into surface portions of said semiconductor substrate via the etched portion of said anti-oxidative layer.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-01-26 | 2001-07-28 | 2002-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-26 | 2005-07-28 | 2006-01-27 | $3760.00 | Window Closed / Lapsed |
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