System and method for asynchronous dual bus conversion using double state machines

Claim 2

A bus interface system in communication with first and second computer components, comprising: a first bus associated with said first component, said first bus having a first characteristic speed, data width, and protocol; a second bus associated with said second component, said second bus having a second characteristic speed, data width, and protocol, wherein at least one of said second characteristics is different from said first characteristics; a first state machine communicating with said first bus, the first state machine being a mirror of a state machine of the first component; a second state machine communicating with said second bus; and data storage means associated with said first and second buses, said first and second state machines being in selective communication using an asynchronous handshaking protocol, whereby data is transferred between said first and second buses.

Claim 3

A system as in claim 1, wherein the second state machine is a mirror of a state machine of the second component.

Claim 4

A system as in claim 2, wherein the handshaking protocol comprises means for producing an asynchronous request signal requesting a data transfer in a format comprising said first characteristics, and means for producing an asynchronous reply signal in a format comprising said second characteristics indicating that data has been sent or is available.

Claim 5

In a computer system having a first bus having a first characteristic speed, data width, and protocol, and a second bus having a second characteristic speed, data width, and protocol, wherein at least one of said second characteristics is different than said first characteristics, a method of asynchronous dual bus conversion using first and second pseudo state machines, the method comprising the steps of: storing data to be transferred in a data storage means; initiating an asynchronous request signal by the first pseudo state machine in communication with a first state machine through the first bus, said first pseudo state machine being a mirror of said first state machine, said asynchronous request signal having a format comprising said first characteristics, thereby requesting that data in the data storage means be transferred; and initiating an asynchronous reply signal by the second pseudo state machine in communication with a second state machine through the second bus, said asynchronous reply signal having a format comprising said second characteristics, thereby signalling that the data has been sent or is available.

Claim 6

In a computer system having a first bus having a first characteristic speed, data width, and protocol, and a second bus having a second characteristic speed, data width, and protocol, wherein at least one of said second characteristics is different than said first characteristics, a method of asynchronous dual bus conversion using first and second pseudo state machines, the method comprising the steps of: storing data to be transferred in a data storage means; initiating an asynchronous request signal by the first pseudo state machine in communication with a first state machine through the first bus, said first pseudo state machine being a mirror of said first state machine, said asynchronous request signal having a format comprising said first characteristics, thereby requesting that data in the data storage means be transferred; and initiating an asynchronous reply signal by the second pseudo state machine in communication with a second state machine through the second bus, said asynchronous reply signal having a format comprising said second characteristics, thereby signalling that the data has been sent or is available.

Claim 7

An interface device for coupling a first state machine with a second state machine, said first state machine having a first characteristic speed, data width and protocol, said second state machine having a second characteristic speed, data width and protocol, at least one said second characteristic being different than one said first characteristic, said interface device comprising: a first pseudo state machine for communicating with said first state machine, said first pseudo state machine determining the state of said first state machine and entering a state responsive to the determined state of said first state machine; and a second pseudo state machine for communicating with said second state machine and with said first pseudo state machine, said second pseudo state machine determining the state of said second state machine and entering a state responsive to the determined state of said second state machine, whereby said first state machine communicates with said second state machine.

Claim 8

An interface device for coupling a first state machine with a second state machine, said first state machine having a first characteristic speed, data width and protocol, said second state machine having a second characteristic speed, data width and protocol, at least one said second characteristic being different than one said first characteristic, said interface device comprising: a first pseudo state machine for communicating with said first state machine, said first pseudo state machine determining the state of said first state machine and entering a state responsive to the determined state of said first state machine; and a second pseudo state machine for communicating with said second state machine and with said first pseudo state machine, said second pseudo state machine determining the state of said second state machine and entering a state responsive to the determined state of said second state machine, whereby said first state machine communicates with said second state machine.

Claim 9

The interface device of claim 5 wherein said interface device is a CPU interface, said first state machine is a microprocessor and said second state machine is a computer system, the second pseudo state machine being connectable to a bus of said computer system.

Claim 10

The CPU interface of claim 6 wherein the microprocessor speed is greater than the bus speed.

Claim 11

The CPU interface of claim 6 wherein the microprocessor data width is wider than that of the bus.

Claim 12

The CPU interface of claim 8 wherein the microprocessor data width is twice that of the bus.

Claim 13

The CPU interface of claim 9 wherein the microprocessor is a first microprocessor and the bus is a microprocessor bus for a second microprocessor, the first microprocessor speed being greater than the second microprocessor speed.

Claim 14

A CPU assembly comprising: a microprocessor, said microprocessor being a processor state machine and having a characteristic speed, data width and protocol; data storage means associated with said microprocessor; a first pseudo state machine mirroring said processor state machine and communicating with said microprocessor and said data storage means; and a second pseudo state machine communicating with said first pseudo state machine and coupling said first pseudo state machine to a bus, said bus having a characteristic speed, data width and protocol, at least one said bus characteristic being different than said microprocessor's characteristics, whereby data is transferred between said microprocessor and said bus.

Claim 15

A CPU assembly comprising: a microprocessor, said microprocessor being a processor state machine and having a characteristic speed, data width and protocol; data storage means associated with said microprocessor; a first pseudo state machine mirroring said processor state machine and communicating with said microprocessor and said data storage means; and a second pseudo state machine communicating with said first pseudo state machine and coupling said first pseudo state machine to a bus, said bus having a characteristic speed, data width and protocol, at least one said bus characteristic being different than said microprocessor's characteristics, whereby data is transferred between said microprocessor and said bus.

Claim 16

The CPU assembly of claim 11 wherein the microprocessor speed is greater than the bus speed.

Claim 17

The CPU assembly of claim 11 wherein the microprocessor data width is wider than that of the bus.

Claim 18

The CPU assembly of claim 13 wherein the microprocessor data width is twice that of the bus.

Claim 19

The CPU assembly of claim 14 wherein the microprocessor speed is greater than the bus speed.