Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus

Claim 1

A processing unit coupled to a system bus for transferring and receiving requests, said processing unit comprising: a synchronous local bus; a microprocessor including a synchronous independently operated microprocessor bus state machine coupled to said synchronous local bus for controlling access to said synchronous local bus according to a predetermined protocol; a local memory tightly coupled to said synchronous local bus, said memory including a synchronous independently operated memory state machine for controlling processing of local commands received from said microprocessor and external commands received from said system bus; a synchronous independently operated processor state machine tightly coupled to said synchronous local bus and to said system bus for controlling transfer of microprocessor issued read and write commands from said synchronous local bus to said system bus; and a synchronous independently operated external state machine tightly coupled to said synchronous local bus and to said system bus for controlling the transfer of external read and write commands received from said system bus to said local memory, each of said state machines including synchronizing circuit means for generating signals to selectively interconnect different ones of said state machines together for sharing access to said local bus without interference to enable optimum performance in processing commands.