US5710075A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method to increase surface area of a storage node electrode, of an STC structure, for DRAM devices
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1996-11-06
•
Granted: 1998-01-20
•
Expires: 2016-11-06
Abstract
Abstract A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a lower, or storage node electrode, for the STC structure, consisting of a flat, lower polysilicon shape, contacting an underlying transistor region, and of an upper polysilicon shape, comprised of polysilicon spacers, on the sides of the lower polysilicon shape, protruding above the top surface of the flat, lower polysilicon shape. The polysilicon spacers are formed via LPCVD and anisotropic RIE procedures, in addition to the use of a lift off procedure, used to remove unwanted polysilicon spacers from an underlying silicon oxide surface. This storage node configuration results in an significant increase of surface area, when compared to storage nodes fabricated without the incorporation of polysilicon spacers.
Inventors
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:35
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
546 words
A method of fabricating a DRAM device, on a semiconductor substrate, comprised of underlying transistors; with gate insulators, gate electrode structures, formed from a first silicon oxide, and a first polysilicon layer, insulator sidewall spacers, formed from a second silicon oxide layer, and source and drain regions, and an overlying STC structure; with a storage node electrode, a dielectric layer, and an overlying plate electrode, and with said storage node electrode, comprised of a lower polysilicon shape, contacting said source and drain regions of said underlying transistor, and with polysilicon spacers, protruding above the top surface of said lower polysilicon shape, comprising the steps of: depositing third silicon oxide layer, on said underlying transistor of said DRAM device; depositing a first silicon nitride layer on said third silicon oxide layer; opening a contact hole, in said first silicon nitride layer, and in said third silicon oxide layer, to expose top surface of said source and drain regions, of said underlying transistor; depositing a second polysilicon layer on top surface of said first silicon nitride layer, and on top surface of said source and drain regions, exposed in said contact hole; depositing a second silicon nitride layer on said second polysilicon layer; patterning to create a electrode opening in said second silicon nitride layer, and in a top portion of said second polysilicon layer; depositing a fourth silicon oxide layer on the top surface of said second silicon nitride layer, and on the exposed surfaces of said electrode opening; anisotropic etching of said fourth silicon oxide layer, to form silicon oxide spacers on the sides of said second polysilicon layer, exposed in said electrode opening; growing a silicon oxide plug, on surface of said second polysilicon layer, exposed between silicon oxide spacers, in said electrode opening; removal of said second silicon nitride layer from the top surface of said second polysilicon layer, exposing said second polysilicon layer in regions not covered by said silicon oxide spacers, or by said silicon oxide plugs; anisotropic etching of said second polysilicon layer, in regions not covered by said silicon oxide spacers, or silicon oxide plugs, creating said lower polysilicon shape, of said storage node electrode, with said silicon oxide spacers, and said silicon oxide plug, between said silicon oxide spacers, on said lower polysilicon shape; depositing a third polysilicon layer on said silicon oxide spacers, on said silicon oxide plug, between said silicon oxide spacers, and on second silicon nitride layer between said lower polysilicon shapes; anisotropic etching of said third polysilicon layer, to form said polysilicon spacers, overlying said first silicon nitride layer, on the exterior sides of said silicon oxide spacers, and forming polysilicon spacers, overlying said silicon oxide plug, on the interior sides of said silicon oxide spacers; isotropic removal of said silicon oxide spacers, and of said silicon oxide plugs, also lifting off said polysilicon spacers that overlaid said silicon oxide plug, forming said storage node electrode, comprised of said lower polysilicon shape, and said polysilicon spacers, on the sides of said lower polysilicon shape, and protruding above, said lower polysilicon shape; forming said dielectric layer on said storage node electrode; depositing a fourth polysilicon layer on said dielectric layer; and patterning of said fourth polysilicon layer to form said plate electrode, of said STC structure.
Claim 2
Independent Claim
546 words
A method of fabricating a DRAM device, on a semiconductor substrate, comprised of underlying transistors; with gate insulators, gate electrode structures, formed from a first silicon oxide, and a first polysilicon layer, insulator sidewall spacers, formed from a second silicon oxide layer, and source and drain regions, and an overlying STC structure; with a storage node electrode, a dielectric layer, and an overlying plate electrode, and with said storage node electrode, comprised of a lower polysilicon shape, contacting said source and drain regions of said underlying transistor, and with polysilicon spacers, protruding above the top surface of said lower polysilicon shape, comprising the steps of: depositing third silicon oxide layer, on said underlying transistor of said DRAM device; depositing a first silicon nitride layer on said third silicon oxide layer; opening a contact hole, in said first silicon nitride layer, and in said third silicon oxide layer, to expose top surface of said source and drain regions, of said underlying transistor; depositing a second polysilicon layer on top surface of said first silicon nitride layer, and on top surface of said source and drain regions, exposed in said contact hole; depositing a second silicon nitride layer on said second polysilicon layer; patterning to create a electrode opening in said second silicon nitride layer, and in a top portion of said second polysilicon layer; depositing a fourth silicon oxide layer on the top surface of said second silicon nitride layer, and on the exposed surfaces of said electrode opening; anisotropic etching of said fourth silicon oxide layer, to form silicon oxide spacers on the sides of said second polysilicon layer, exposed in said electrode opening; growing a silicon oxide plug, on surface of said second polysilicon layer, exposed between silicon oxide spacers, in said electrode opening; removal of said second silicon nitride layer from the top surface of said second polysilicon layer, exposing said second polysilicon layer in regions not covered by said silicon oxide spacers, or by said silicon oxide plugs; anisotropic etching of said second polysilicon layer, in regions not covered by said silicon oxide spacers, or silicon oxide plugs, creating said lower polysilicon shape, of said storage node electrode, with said silicon oxide spacers, and said silicon oxide plug, between said silicon oxide spacers, on said lower polysilicon shape; depositing a third polysilicon layer on said silicon oxide spacers, on said silicon oxide plug, between said silicon oxide spacers, and on second silicon nitride layer between said lower polysilicon shapes; anisotropic etching of said third polysilicon layer, to form said polysilicon spacers, overlying said first silicon nitride layer, on the exterior sides of said silicon oxide spacers, and forming polysilicon spacers, overlying said silicon oxide plug, on the interior sides of said silicon oxide spacers; isotropic removal of said silicon oxide spacers, and of said silicon oxide plugs, also lifting off said polysilicon spacers that overlaid said silicon oxide plug, forming said storage node electrode, comprised of said lower polysilicon shape, and said polysilicon spacers, on the sides of said lower polysilicon shape, and protruding above, said lower polysilicon shape; forming said dielectric layer on said storage node electrode; depositing a fourth polysilicon layer on said dielectric layer; and patterning of said fourth polysilicon layer to form said plate electrode, of said STC structure.
Claim 3
Dependent Claim
33 words
The method of claim 1, wherein said second polysilicon layer is deposited using LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 4000 to 8000 Angstroms.
Claim 4
Dependent Claim
37 words
The method of claim 1, wherein said second silicon nitride layer is deposited using either LPCVD or PECVD procedures, at a temperature between about 700° to 750° C., to a thickness between about 500 to 1500 Angstroms.
Claim 5
Dependent Claim
46 words
The method of claim 1, wherein said electrode opening is formed via RIE processing of said second silicon nitride layer using CHF 3 as an etchant, then using Cl 2 as an etchant to RIE between about 2000 to 6000 Angstroms, of said second polysilicon layer.
Claim 6
Dependent Claim
36 words
The method of claim 1, wherein said fourth silicon oxide layer is deposited using LPCVD or PECVD procedures, at a temperature between about 700° to 750° C., to a thickness between about 800 to 2500 Angstroms.
Claim 7
Dependent Claim
27 words
The method of claim 1, wherein said silicon oxide spacers are formed via anisotropic RIE, of said fourth silicon oxide layer, using CHF 3 as an etchant.
Claim 8
Dependent Claim
38 words
The method of claim 1, wherein said silicon oxide plug is formed via thermal oxidation procedures, in an oxygen-steam ambient, at a temperature between about 800° to 900° C., to a thickness between about 300 to 1000 Angstroms.
Claim 9
Dependent Claim
28 words
The method of claim 1, wherein said second silicon nitride layer is removed using a hot phosphoric acid solution, at a temperature between about 140° to 180° C.
Claim 10
Dependent Claim
31 words
The method of claim 1, wherein said lower polysilicon shape, of said storage node electrode, is formed via anisotropic, RIE of said second polysilicon layer, using Cl 2 as an etchant.
Claim 11
Dependent Claim
33 words
The method of claim 1, wherein said third polysilicon layer is deposited via LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 500 to 2000 Angstroms.
Claim 12
Dependent Claim
68 words
The method of claim 1, wherein said polysilicon spacers are formed on the exterior sides of said silicon oxide spacers, overlying said first silicon nitride layer, and polysilicon spacers are formed on the interior sides of said silicon oxide spacers, overlying said silicon oxide plugs, via anisotropic RIE procedures, using Cl 2 as an etchant, with the height of said polysilicon spacers between about 4000 to 8000 Angstroms.
Claim 13
Dependent Claim
44 words
The method of claim 1, wherein said silicon oxide spacers, said silicon oxide plugs, and said polysilicon spacers, overlying said silicon oxide plugs, are removed using a wet buffered, or dilute, hydrofluoric acid solution, or are removed using a dry vapor, hydrofluoric acid procedure.
Claim 14
Dependent Claim
77 words
The method of claim 1, wherein said dielectric layer is ONO, at an equivalent silicon dioxide thickness between about 40 to 80 Angstroms, created by an initial thermal oxidation to form a silicon oxide layer, between about 10 to 50 Angstroms, followed by a deposition of silicon nitride, to a thickness between about 10 to 20 Angstroms, and thermal oxidation of said silicon nitride layer, creating a silicon oxynitride layer, on the underlying, said silicon oxide layer.
Claim 15
Dependent Claim
29 words
The method of claim 1, wherein said dielectric layer is Ta 2 O 5 , obtained via r.f. sputtering techniques, at a thickness between about 10 to 100 Angstroms.
Claim 16
Dependent Claim
44 words
The method of claim 1, wherein said fourth polysilicon layer, used for creation of said plate electrode of said STC structure, is deposited using LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 1000 to 2000 Angstroms.
Claim 17
Independent Claim
536 words
A method of fabricating a stacked capacitor structure, (STC), for a DRAM device, in which the surface area of the storage node electrode is increased via use of a storage node electrode configuration, consisting of a flat, lower polysilicon shape, used for contact to an underlying transistor region, and of an upper polysilicon shape of polysilicon spacers, protruding above the top surface of said flat, lower polysilicon shape, comprising the steps of: depositing a first silicon oxide layer on an underlying transistor structure, of said DRAM device; depositing a first silicon nitride layer on said first silicon oxide layer; opening a contact hole in said first silicon nitride layer, and in said first silicon oxide layer, to expose top surface of said underlying transistor region; depositing a first polysilicon layer on top surface of said first silicon nitride layer, and on said top surface of said underlying transistor region, exposed in said contact hole; depositing a second silicon nitride layer on said first polysilicon layer; patterning to create an electrode opening in said second silicon nitride layer, and into between about 2000 to 6000 Angstroms of a top portion of said first polysilicon layer; depositing a second silicon oxide layer on top surface of said second nitride layer, and on exposed surfaces of said electrode opening; anisotropic etching of said second silicon oxide layer to form silicon oxide spacers on sides of said electrode opening; thermal oxidation of said first polysilicon layer, exposed in said electrode opening, to form silicon oxide plug, between said silicon oxide spacers; removal of said second silicon nitride layer from the top surface of said first polysilicon layer, exposing said first polysilicon layer in regions not covered by said silicon oxide spacers, or by said silicon oxide plug; anisotropic etching of said first polysilicon layer, in regions not covered by said silicon oxide spacers, or by said silicon oxide plugs, creating said flat, lower polysilicon shape, of said storage node electrode, with said silicon oxide spacers, protruding above the top surface of said flat, lower polysilicon shape, and with said silicon oxide plug, on said flat, lower polysilicon shape, between said silicon oxide spacers; depositing a second polysilicon layer on said silicon oxide spacers, and on said silicon oxide plugs, overlying said flat, lower polysilicon shape, and on said second silicon nitride layer, between said flat, lower polysilicon shapes; anisotropic etching of said second polysilicon layer to create polysilicon spacers, on the exterior sides of said silicon oxide spacers, overlying said first silicon nitride layer, and creating polysilicon spacers, on the interior sides of said silicon oxide spacers, overlying said silicon oxide plugs; removal of said silicon oxide spacers, and of said silicon oxide plugs, including removal of said polysilicon spacers residing on said silicon oxide plugs, resulting in formation of said upper polysilicon shape, of said storage node electrode, of said polysilicon spacers, on the sides of said flat, lower polysilicon shape, and protruding above the top surface of said flat, lower polysilicon shape; forming a dielectric layer on top surface of said storage node electrode; depositing a third polysilicon layer on said dielectric layer; and patterning of said third polysilicon layer to form plate electrode, of said STC structure.
Claim 18
Independent Claim
536 words
A method of fabricating a stacked capacitor structure, (STC), for a DRAM device, in which the surface area of the storage node electrode is increased via use of a storage node electrode configuration, consisting of a flat, lower polysilicon shape, used for contact to an underlying transistor region, and of an upper polysilicon shape of polysilicon spacers, protruding above the top surface of said flat, lower polysilicon shape, comprising the steps of: depositing a first silicon oxide layer on an underlying transistor structure, of said DRAM device; depositing a first silicon nitride layer on said first silicon oxide layer; opening a contact hole in said first silicon nitride layer, and in said first silicon oxide layer, to expose top surface of said underlying transistor region; depositing a first polysilicon layer on top surface of said first silicon nitride layer, and on said top surface of said underlying transistor region, exposed in said contact hole; depositing a second silicon nitride layer on said first polysilicon layer; patterning to create an electrode opening in said second silicon nitride layer, and into between about 2000 to 6000 Angstroms of a top portion of said first polysilicon layer; depositing a second silicon oxide layer on top surface of said second nitride layer, and on exposed surfaces of said electrode opening; anisotropic etching of said second silicon oxide layer to form silicon oxide spacers on sides of said electrode opening; thermal oxidation of said first polysilicon layer, exposed in said electrode opening, to form silicon oxide plug, between said silicon oxide spacers; removal of said second silicon nitride layer from the top surface of said first polysilicon layer, exposing said first polysilicon layer in regions not covered by said silicon oxide spacers, or by said silicon oxide plug; anisotropic etching of said first polysilicon layer, in regions not covered by said silicon oxide spacers, or by said silicon oxide plugs, creating said flat, lower polysilicon shape, of said storage node electrode, with said silicon oxide spacers, protruding above the top surface of said flat, lower polysilicon shape, and with said silicon oxide plug, on said flat, lower polysilicon shape, between said silicon oxide spacers; depositing a second polysilicon layer on said silicon oxide spacers, and on said silicon oxide plugs, overlying said flat, lower polysilicon shape, and on said second silicon nitride layer, between said flat, lower polysilicon shapes; anisotropic etching of said second polysilicon layer to create polysilicon spacers, on the exterior sides of said silicon oxide spacers, overlying said first silicon nitride layer, and creating polysilicon spacers, on the interior sides of said silicon oxide spacers, overlying said silicon oxide plugs; removal of said silicon oxide spacers, and of said silicon oxide plugs, including removal of said polysilicon spacers residing on said silicon oxide plugs, resulting in formation of said upper polysilicon shape, of said storage node electrode, of said polysilicon spacers, on the sides of said flat, lower polysilicon shape, and protruding above the top surface of said flat, lower polysilicon shape; forming a dielectric layer on top surface of said storage node electrode; depositing a third polysilicon layer on said dielectric layer; and patterning of said third polysilicon layer to form plate electrode, of said STC structure.
Claim 19
Dependent Claim
33 words
The method of claim 16, wherein said first polysilicon layer is obtained via LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 4000 to 8000 Angstroms.
Claim 20
Dependent Claim
36 words
The method of claim 16, wherein said second silicon nitride layer is deposited using LPCVD or PECVD procedures, at a temperature between about 700° to 750° C., to a thickness between about 500 to 1500 Angstroms.
Claim 21
Dependent Claim
50 words
The method of claim 16, wherein said electrode opening is formed via RIE procedures of said second silicon nitride layer using CHF 3 as an etchant, and then using Cl 2 as an etchant to remove between about 2000 to 6000 Angstroms of said first polysilicon layer, via RIE procedures.
Claim 22
Dependent Claim
36 words
The method of claim 16, wherein said second silicon oxide layer is deposited using LPCVD or PECVD procedures, at a temperature between about 700° to 750° C., to a thickness between about 800 to 2500 Angstroms.
Claim 23
Dependent Claim
28 words
The method of claim 16, wherein said silicon oxide spacers are formed via anisotropic RIE procedures of said second silicon oxide layer using CHF 3 as an etchant.
Claim 24
Dependent Claim
42 words
The method of claim 16, wherein said silicon oxide plug is formed via thermal oxidation of said first polysilicon layer in an oxygen-steam ambient, at a temperature between about 800° to 900° C., to a thickness between about 300 to 1000 Angstroms.
Claim 25
Dependent Claim
26 words
The method of claim 16, wherein said second silicon nitride layer is removed via hot phosphoric acid, at a temperature between about 140° to 180° C.
Claim 26
Dependent Claim
30 words
The method of claim 16, wherein said flat, lower polysilicon shape, is formed via etching of said first polysilicon layer via anisotropic, RIE procedures, using Cl 2 as an etchant.
Claim 27
Dependent Claim
33 words
The method of claim 16, wherein said second polysilicon layer is deposited using LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 500 to 2000 Angstroms.
Claim 28
Dependent Claim
38 words
The method of claim 16, wherein said polysilicon spacers are formed on the sides of said silicon oxide spacers, using Cl 2 as an etchant, with the height of said polysilicon spacers between about 4000 to 8000 Angstroms.
Claim 29
Dependent Claim
35 words
The method of claim 16, wherein said silicon oxide spacers, and said silicon oxide plugs, are removed using a wet buffered, or dilute, hydrofluoric acid solution, or removed using a dry vapor, hydrofluoric acid procedure.
Claim 30
Dependent Claim
75 words
The method of claim 16, wherein said dielectric layer is ONO, with an equivalent silicon oxide thickness between about 40 to 80 Angstroms, created by growing a thin silicon oxide layer on said storage node electrode, at a thickness between about 10 to 50 Angstroms, depositing between about 10 to 20 Angstroms of a silicon nitride layer, and oxidizing said silicon nitride layer to from a silicon oxynitride layer on said thin silicon oxide layer.
Claim 31
Dependent Claim
30 words
The method of claim 16, wherein said thin dielectric layer is Ta 2 O 5 , deposited using r.f. sputtering procedures, to a thickness between about 10 to 100 Angstroms.
Claim 32
Dependent Claim
33 words
The method of claim 16, wherein said third polysilicon layer is deposited using LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 1000 to 2000 Angstroms.
Claim 33
Dependent Claim
24 words
The method of claim 16, wherein said plate electrode is created via RIE of said second polysilicon layer, using Cl 2 as an etchant.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-19 | 2001-07-21 | 2002-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-19 | 2005-07-21 | 2006-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-19 | 2009-07-21 | 2010-01-20 | $7700.00 | Window Closed / Lapsed |