Patent US5708622A successfully refreshed from Google Patents.
US5708622A
Expired / Lapsed
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Clock synchronous semiconductor memory device
Assignee: VACHELLIA LLC
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Filing: 1996-03-14
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Granted: 1998-01-13
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Expires: 2016-03-14
Abstract
Abstract A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.
Inventors
- 👤 Jun Ohtani
- 👤 Akira Yamazaki
- 👤 Katsumi Dosaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:45
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C7/00; G11C7/10; G11C7/1072; G11C11/005; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C7/1015; G11C7/103; G11C7/1051; G11C7/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
155 words
A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells; a first data register for temporarily holding data of a plurality of memory cells selected at a time in said memory cell array; a second data register receiving and storing data held by said first data register; detection means coupled to receive an operation mode instructing signal indicating that said second data register is accessed when active, for detecting that said second data register is under a non-accessed state in response to inactivation of said operation mode instruction signal; and transfer means responsive to detection of non-accessing to said second data register by said detection means and a data transfer instruction signal for conducting data transfer from said first data register to said second data register, said transfer means including means responsive to said detection means detecting that said operation mode instruction signal is active for stopping said data transfer.
Claim 2
Dependent Claim
155 words
A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells; a first data register for temporarily holding data of a plurality of memory cells selected at a time in said memory cell array; a second data register receiving and storing data held by said first data register; detection means coupled to receive an operation mode instructing signal indicating that said second data register is accessed when active, for detecting that said second data register is under a non-accessed state in response to inactivation of said operation mode instruction signal; and transfer means responsive to detection of non-accessing to said second data register by said detection means and a data transfer instruction signal for conducting data transfer from said first data register to said second data register, said transfer means including means responsive to said detection means detecting that said operation mode instruction signal is active for stopping said data transfer.
Claim 3
Dependent Claim
46 words
A semiconductor memory device as recited in claim 1, wherein said transfer means further includes means for maintaining said first data register and said second register electrically in contact with each other until another data transfer instruction signal is given after the data transfer is completed.
Claim 4
Dependent Claim
110 words
A semiconductor memory device as recited in claim 1, wherein said transfer means further includes, clock generation means for generating a clock signal, detection means for detecting a data read instruction being given, count means including a plurality of cascade-connected binary counters and activated in response to a detection signal from said detection means for counting said clock signal, gate means responsive to a countup of a prescribed number of said clock signals by said count means for generating said data transfer instruction signal, and reset means responsive to said data read instruction for resetting counters other than a 1-bit binary counter in a first stage of said count means.
Claim 5
Dependent Claim
46 words
A semiconductor memory device as recited in claim 3, wherein said detection means disables said gate means in response to said operation mode instructing signal indicating that said second data register is accessed, for inhibiting generation of said data transfer instruction signal from said gate means.
Claim 6
Dependent Claim
81 words
A semiconductor memory device according to claim 1, further comprising; another memory cell array having a plurality of memory cells arranged in rows and columns; an output buffer for supplying an external data, first transmission means responsive to a first transfer designating signal for transmitting data held in said second data register to said another memory array, and second transmission means responsive to a second transfer designating signal for transmitting data held in said second data register to said output buffer.
Claim 7
Dependent Claim
32 words
A semiconductor memory device according to claim 5, further comprising, selection means responsive to an address signal for selecting an output of said second transmission means for transmission to said output buffer.
Claim 8
Dependent Claim
61 words
The semiconductor memory device according to claim 1, wherein said transfer means includes means responsive to said detection means detecting that said second data register is under an accessed state, for stopping activation of said data transfer instructing signal while said second data register is under the accessed state, the activation of said data transfer instructing signal instructing the data transfer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-12 | 2001-07-14 | 2002-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-12 | 2005-07-14 | 2006-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-12 | 2009-07-14 | 2010-01-13 | $7700.00 | Window Closed / Lapsed |