Semiconductor memory device having shared sense amplifier arrays individually controlled for cache storage

Claim 2

A semiconductor memory device comprising: a memory cell array including a plurality of memory cell blocks formed by memory cells arranged in an array in a row direction and a column direction, a plurality of bit line pairs connected to columns of said memory cells, respectively, and a plurality of word lines connected to rows of said memory cells, respectively; and a plurality of sense amplifiers connected to ends of said plurality of bit line pairs, respectively, and responsive to an activation signal for magnifying potential differences on said plurality of bit line pairs, said plurality of sense amplifiers being divided into a plurality of sense amplifier groups each shared between an adjacent two of said plurality of memory cell blocks so as to be used by a selected one of said adjacent two of said plurality of memory cell blocks, said plurality of sense amplifier groups forming a cache storage so that data is read out from said plurality of sense amplifiers when a row address selected in a data access operation to said memory cells is matched with a row address assigned to a row of memory cells supplying said data to said plurality of sense amplifiers, said plurality of sense amplifier groups being individually controlled during an access to said cache storage.

Claim 3

A semiconductor memory device comprising: a memory cell array including a plurality of memory cell blocks each having memory cells arranged in rows and columns; a plurality of bit line pair groups respectively associated with said plurality of memory cell blocks, the bit line pairs of each of said plurality of bit line pair groups being respectively connected to columns of said memory cells of an associated one of said plurality of memory cell blocks; a plurality of word lines respectively coupled to rows of said memory cells of said plurality of memory cell blocks, and selectively energized so as to read out data bits to associated bit line pairs; a plurality of sense amplifier units including shared sense amplifier units each shared between two of said plurality of bit line pair groups, and responsive to an activation signal of an active level so that two of said plurality of sense amplifier units amplify said data bits on the associated bit line pairs, said plurality of sense amplifier units forming a cache storage for maintaining said data bits while said activation signal remains in said active level; a decision means for checking an address signal indicative of a first address for data to be accessed from one of said plurality of memory cell blocks to determine whether or not said data to be accessed is stored in one of said plurality of sense amplifier units, said decision means producing a hit signal if said data to be accessed is stored in said one of said plurality of sense amplifier units; and a controlling means responsive to said hit signal for reading out said data bits from said one of said plurality of sense amplifier units without energizing said plurality of word lines, said controlling means electrically connecting two of said plurality of sense amplifier units to said one of said plurality of memory cell blocks before selectively energizing said plurality of word lines in the absence of said hit signal.

Claim 4

A semiconductor memory device comprising: a memory cell array including a plurality of memory cell blocks each having memory cells arranged in rows and columns; a plurality of bit line pair groups respectively associated with said plurality of memory cell blocks, the bit line pairs of each of said plurality of bit line pair groups being respectively connected to columns of said memory cells of an associated one of said plurality of memory cell blocks; a plurality of word lines respectively coupled to rows of said memory cells of said plurality of memory cell blocks, and selectively energized so as to read out data bits to associated bit line pairs; a plurality of sense amplifier units including shared sense amplifier units each shared between two of said plurality of bit line pair groups, and responsive to an activation signal of an active level so that two of said plurality of sense amplifier units amplify said data bits on the associated bit line pairs, said plurality of sense amplifier units forming a cache storage for maintaining said data bits while said activation signal remains in said active level; a decision means for checking an address signal indicative of a first address for data to be accessed from one of said plurality of memory cell blocks to determine whether or not said data to be accessed is stored in one of said plurality of sense amplifier units, said decision means producing a hit signal if said data to be accessed is stored in said one of said plurality of sense amplifier units; and a controlling means responsive to said hit signal for reading out said data bits from said one of said plurality of sense amplifier units without energizing said plurality of word lines, said controlling means electrically connecting two of said plurality of sense amplifier units to said one of said plurality of memory cell blocks before selectively energizing said plurality of word lines in the absence of said hit signal.

Claim 5

The semiconductor memory device as set forth in claim 2, in which said decision means includes: a plurality of registers respectively associated with said plurality of sense amplifier units so as to respectively store second addresses assigned to rows of memory cells supplying data bits to said plurality of sense amplifier units in a rewritable manner, a comparator means for comparing said first address with the second addresses for producing said hit signal; and a plurality of selector units selectively coupled between said plurality of registers and said comparator means so as to supply said second addresses from two of said plurality of registers corresponding to said two of said plurality of sense amplifier units to said comparator means.

Claim 6

The semiconductor memory device as set forth in claim 3, in which said decision means further includes: a logic gate coupled to said comparator means for producing a mis-hit signal when said second addresses are different from said first address, said controlling means being responsive to said mis-hit signal for coupling said two of said plurality of sense amplifier units to said one of said plurality of memory cell blocks.