Semiconductor memory and method of using the same, column decoder, and image processor

Claim 2

A semiconductor memory comprising: a memory cell array having a plurality of memory cell blocks in each of which a single or a plurality of memory cells arranged in a column direction are connected to a sub word line, said plurality of memory cell blocks being arranged in an array; horizontal word lines extending in horizontal directions and diagonal word lines extending in diagonal directions; and a word-line selecting means for receiving a word-line select signal, selecting a given one of said horizontal or diagonal word lines based on the word-line select signal which has been received, and connecting the selected word line to said sub word line in each of the memory cell blocks corresponding to the word line, wherein those ones of said plurality of memory cell blocks which are arranged in one of the horizontal directions or in one of the diagonal directions are selected based on the word-line select signal and sets of data in the plurality of memory cells in the plurality of selected memory cell blocks arranged in the horizontal direction or in the diagonal direction are outputted onto respective pairs of bit lines.

Claim 3

A semiconductor memory according to claim 1, wherein the word-line selecting means comprises a word-line selecting circuit having an input connected to one of the horizontal word lines and one of the diagonal word lines and having an output connected to the corresponding sub word line, while receiving the word-line select signal, selecting either one of said horizontal word line and said diagonal word line based on the word-line select signal which has been received, and connecting the selected word line to said sub word line.

Claim 4

A semiconductor memory according to claim 1, further comprising: a serial access memory for receiving and storing a plurality of signals, said plurality of stored signals being sequentially accessed in accordance with a serial clock; and a transfer means for transferring and inputting signals on the plurality of bit lines to said serial access memory.

Claim 5

A method of using the semiconductor memory according to claim 1, wherein a large number of sets of data are stored in the memory cells of the semiconductor memory and the horizontal word lines extending in the horizontal directions and the diagonal word lines extending in the diagonal directions are provided, said method comprising the steps of: sequentially storing, in the memory cells of the memory cell blocks arranged in a given column, a set of data in a rectangular region in which the number in a column direction of the memory cells constituting each of the memory cell blocks is used as a number in a column direction and the number in a row direction of the memory cell blocks is used as a number in a row direction, said step being repeatedly performed; and in storing the set of data in said rectangular region, storing the set of data in the column corresponding to the rectangular region in the memory cell blocks selected by one of the diagonal word lines.

Claim 6

An image processor comprising: a semiconductor memory comprising a memory cell array having a plurality of memory cell blocks in each of which a single or a plurality of memory cells arranged in a column direction are connected to a sub word line, said plurality of memory cell blocks being arranged in an array, horizontal word lines extending in horizontal directions and diagonal word lines extending in diagonal directions, and a word-line selecting means for receiving a word-line select signal, selecting a given one of said horizontal or diagonal word lines based on the word-line select signal which has been received, and connecting the selected word line to said sub word line in each of the memory cell blocks corresponding to the word line, wherein those ones of said plurality of memory cell blocks which are arranged in one of the horizontal directions or in one of the diagonal directions are selected based on the word-line select signal and sets of data in the plurality of memory cells in the plurality of selected memory cell blocks arranged in the horizontal direction or in the diagonal direction are outputted onto a pair of bit lines; a register file composed of a plurality of line registers for receiving and storing sets of data from the bit lines of said semiconductor memory; and a parallel arithmetic unit having a plurality of arithmetic circuits each for fetching in parallel the sets of data stored in the line registers of said register file and performing an arithmetic operation using the sets of fetched data.

Claim 7

An image processor comprising: a semiconductor memory comprising a memory cell array having a plurality of memory cell blocks in each of which a single or a plurality of memory cells arranged in a column direction are connected to a sub word line, said plurality of memory cell blocks being arranged in an array, horizontal word lines extending in horizontal directions and diagonal word lines extending in diagonal directions, and a word-line selecting means for receiving a word-line select signal, selecting a given one of said horizontal or diagonal word lines based on the word-line select signal which has been received, and connecting the selected word line to said sub word line in each of the memory cell blocks corresponding to the word line, wherein those ones of said plurality of memory cell blocks which are arranged in one of the horizontal directions or in one of the diagonal directions are selected based on the word-line select signal and sets of data in the plurality of memory cells in the plurality of selected memory cell blocks arranged in the horizontal direction or in the diagonal direction are outputted onto a pair of bit lines; a register file composed of a plurality of line registers for receiving and storing sets of data from the bit lines of said semiconductor memory; and a parallel arithmetic unit having a plurality of arithmetic circuits each for fetching in parallel the sets of data stored in the line registers of said register file and performing an arithmetic operation using the sets of fetched data.

Claim 8

An image processor according to claim 5, further comprising a reading means for serially reading the set of data stored in one of the line registers of the register file.

Claim 9

An image processor according to claim 5, further comprising an inputting means for serially inputting the set of data to one of the line registers of the register file.