US5704033A
Expired / Lapsed
US
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Apparatus and method for testing a program memory for a one-chip microcomputer
Assignee: Intellectual Ventures II LLC
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Filing: 1995-10-06
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Granted: 1997-12-30
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Expires: 2015-10-06
Abstract
Abstract In an apparatus of testing a program memory for a one-chip microcomputer which allows the test of program memory mounted within the microcomputer and the test of another function block, thereby reducing test time, and the method therefor, the testing apparatus includes a central processing unit (CPU) for controlling the overall system, an interrupt controller for controlling an interrupt function, a data memory for storing information on data, a peripheral unit connected to a main system for performing input and output functions, a program memory for storing each program information having a predetermined pattern, an address counter for setting address of program memory via an address bus line switched by a first switch, a check-sum calculator for calculating and storing the entire data of the set address of program memory via a data bus line switched by a second switch, a test mode switch for controlling first and second switches, and address counter, and an input/output port for inputting or outputting port outputs of the entire data of check-sum calculator and data of the overall system. Tests for various functional blocks except the program memory are simultaneously performed while performing a test for the program memory. Therefore, the test time and the test cost due to large program memories can be reduced.
Inventors
- 👤 Young Seung Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:10
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/38; G11C29/40
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
199 words
An apparatus for testing a program memory of a microcomputer, the microcomputer including a central processing unit, an interrupt controller for controlling an interrupt function, a data memory for storing information and data, a peripheral unit for performing input and output functions, an address bus line, a data bus line, and an input/output port for inputting and outputting data, the apparatus comprising: a program memory for storing information therein; address counting means for setting an address of said program memory and incrementing the set address by a predetermined value; a first switch for selectively connecting said address counting means, said program memory, and the address bus line; a second switch for selectively connecting said program memory, the data bus line, and check-sum calculator means; the check-sum calculator means for calculating a check-sum value of data stored in the addresses of said program memory set and incremented by said address counting means; mode setting means for setting a test mode and enabling said address counting means, said first switch, and said second switch when the test mode is set; and test means for performing tests on other units of the microcomputer while said check-sum calculator means calculates the check-sum value.
Claim 2
Independent Claim
199 words
An apparatus for testing a program memory of a microcomputer, the microcomputer including a central processing unit, an interrupt controller for controlling an interrupt function, a data memory for storing information and data, a peripheral unit for performing input and output functions, an address bus line, a data bus line, and an input/output port for inputting and outputting data, the apparatus comprising: a program memory for storing information therein; address counting means for setting an address of said program memory and incrementing the set address by a predetermined value; a first switch for selectively connecting said address counting means, said program memory, and the address bus line; a second switch for selectively connecting said program memory, the data bus line, and check-sum calculator means; the check-sum calculator means for calculating a check-sum value of data stored in the addresses of said program memory set and incremented by said address counting means; mode setting means for setting a test mode and enabling said address counting means, said first switch, and said second switch when the test mode is set; and test means for performing tests on other units of the microcomputer while said check-sum calculator means calculates the check-sum value.
Claim 3
Dependent Claim
28 words
An apparatus of claim 1, wherein the predetermined value is one and said address counting means stops incrementing once a last address of said program memory is detected.
Claim 4
Dependent Claim
32 words
An apparatus of claim 1, wherein said check-sum calculator means outputs the check-sum value through the input/output port, after said test means perform the tests on the other units of the microcomputer.
Claim 5
Dependent Claim
25 words
An apparatus of claim 3, wherein the check-sum value is compared with an expected value to determine whether the microcomputer is in a predetermined condition.
Claim 6
Dependent Claim
23 words
An apparatus of claim 4, wherein based on the comparison result, an analysis test on the addresses of said program memory is performed.
Claim 7
Dependent Claim
13 words
An apparatus of claim 5, wherein the analysis test is a user's option.
Claim 8
Dependent Claim
64 words
An apparatus of claim 1, wherein the check-sum value is compared with an expected value to determine whether the microcomputer is in a predetermined condition, said mode setting means resetting the test mode and said address counting means resetting the address of said program memory, based on the comparison result, so as to perform an analysis test on the addresses of said program memory.
Claim 9
Independent Claim
193 words
A method for testing a program memory of a microcomputer, the microcomputer including a central processing unit, an interrupt controller for controlling an interrupt function, a data memory for storing data, a peripheral unit for performing input and output functions, a program memory for storing information therein, an address bus line, a data bus line, and an input/output port for inputting and outputting data, the method comprising the steps of: setting an address of the program memory and incrementing the set address by a predetermined value, using an address counting circuit; providing a first switch for selectively connecting the address counting circuit, the program memory, and the address bus line; providing a second switch for selectively connecting the program memory, the data bus line, and a check-sum calculating circuit; calculating by using the check-sum calculating circuit a check-sum value of data stored in the addresses of the program memory set and incremented by the address counting circuit; setting a test mode and enabling the address counting circuit, the first switch, and the second switch when the test mode is set; and performing tests on other units of the microcomputer during said calculating step.
Claim 10
Independent Claim
193 words
A method for testing a program memory of a microcomputer, the microcomputer including a central processing unit, an interrupt controller for controlling an interrupt function, a data memory for storing data, a peripheral unit for performing input and output functions, a program memory for storing information therein, an address bus line, a data bus line, and an input/output port for inputting and outputting data, the method comprising the steps of: setting an address of the program memory and incrementing the set address by a predetermined value, using an address counting circuit; providing a first switch for selectively connecting the address counting circuit, the program memory, and the address bus line; providing a second switch for selectively connecting the program memory, the data bus line, and a check-sum calculating circuit; calculating by using the check-sum calculating circuit a check-sum value of data stored in the addresses of the program memory set and incremented by the address counting circuit; setting a test mode and enabling the address counting circuit, the first switch, and the second switch when the test mode is set; and performing tests on other units of the microcomputer during said calculating step.
Claim 11
Dependent Claim
31 words
A method of claim 8, wherein the predetermined value is one, and the address counting circuit stops performing said incrementing step once a last address of the program memory is detected.
Claim 12
Dependent Claim
21 words
A method of claim 8, wherein the check-sum calculating outputs the check-sum value through the input/output port, after said performing step.
Claim 13
Dependent Claim
33 words
A method of claim 10, further comprising the steps of: comparing the check-sum value with an expected value; and determining whether the microcomputer is in a predetermined condition based on the comparison result.
Claim 14
Dependent Claim
25 words
A method of claim 11, further comprising the step of: performing an analysis test on addresses of the program memory based on the comparison result.
Claim 15
Dependent Claim
13 words
A method of claim 12, wherein the analysis test is a user's option.
Claim 16
Dependent Claim
35 words
A method of claim 8, further comprising the steps of: comparing the check-sum value with an expected value; and resetting a test mode and an address of the program memory based on the comparison result.
Claim 17
Dependent Claim
25 words
A method of claim 14, further comprising the step of: performing an analysis test on the addresses of the program memory after said resetting step.
Claim 18
Dependent Claim
54 words
A method of claim 15, wherein said step of performing the analysis test includes the steps of: sequentially outputting data of the program memory stored in the addresses of the program memory, comparing the output data with predetermined values, and detecting defects in the addresses of the program memory based on the comparison result.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-29 | 2001-06-30 | 2001-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-29 | 2005-06-30 | 2005-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-29 | 2009-06-30 | 2009-12-30 | $7700.00 | Window Closed / Lapsed |