US5703974A
Expired / Lapsed
US
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Semiconductor photonic integrated circuit and fabrication process therefor
Assignee: NEC Corp
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Filing: 1996-07-12
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Granted: 1997-12-30
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Expires: 2016-07-12
Abstract
Abstract On a surface of an n-InP substrate, a mask of SiO 2 layer wide in an active region and narrow in a passive region and having a constant gap width. In a waveguide region defined between the masks, a waveguide structure constituted of an n-InGaAsP guide layer, an undoped InGaAsP optical waveguide layer and a p-InP clad layer is selectively grown to form. Again, utilizing SiO 2 layer, a mask is formed on the surface of the p-InP layer in the active region and a pair of masks defining the waveguide structure is formed in a the passive region, and high resistance InP layer is grown. Also, in the active region, a p-InP layer, a p-InGaAs contact layer are selectively grown. By forming SiO 2 , a window is formed to form p-side electrode. An n-type electrode is formed on the back surface of the substrate, By this, a device having an optical loss in the active region and passive region becomes low, a coupling coefficient between both regions is high. Also, an element capacitance can become small to enable high speed operation.
Inventors
- 👤 Tatsuya Sasaki
- 👤 Takeshi Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:40
CPC Classifications
G; G02; G02B; G02B6/00; G02B6/10; G02B6/12; G02B6/12004; H; H01; H01S; H01S5/00; H01S5/02; H01S5/026; G02B2006/12083; G02B2006/12121; G02B2006/12123; G02B2006/12166; G02B2006/12195; H01S5/0265; H01S5/06; H01S5/062; H01S5/0625; H01S5/06255; H01S5/06256; H01S5/20; H01S5/2054; H01S5/2077; H01S5/40; H01S5/4025; H01S5/50
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
121 words
A semiconductor photonic integrated circuit comprising: a first conductive type semiconductor substrate having first region and a second region on the surface thereof; a first optical waveguide layer formed in mesa form on said first region of said first conductivity type semiconductor substrate; a second optical waveguide layer formed continuously with said first optical waveguide layer, of a material having larger bandgap energy than said first optical waveguide layer within said second region on said first conductivity type semiconductor substrate; a high resistance semiconductor layer covering a side surface of said first optical waveguide layer and an upper surface of said second optical waveguide layer; and a second conductivity type semiconductor layer covering an upper surface of said first optical waveguide.
Claim 2
Dependent Claim
121 words
A semiconductor photonic integrated circuit comprising: a first conductive type semiconductor substrate having first region and a second region on the surface thereof; a first optical waveguide layer formed in mesa form on said first region of said first conductivity type semiconductor substrate; a second optical waveguide layer formed continuously with said first optical waveguide layer, of a material having larger bandgap energy than said first optical waveguide layer within said second region on said first conductivity type semiconductor substrate; a high resistance semiconductor layer covering a side surface of said first optical waveguide layer and an upper surface of said second optical waveguide layer; and a second conductivity type semiconductor layer covering an upper surface of said first optical waveguide.
Claim 3
Dependent Claim
68 words
A semiconductor photonic integrated circuit as set forth in claim 1, wherein said second optical waveguide is formed into a mesa form having width substantially equal to that of said first optical waveguide or a width gradually reducing from a substantially equal width to that of said first optical waveguide, and a side surface of said second optical waveguide layer is covered with said high resistance semiconductor layer.
Claim 4
Dependent Claim
56 words
A semiconductor photonic integrated circuit as set forth in claim 1, wherein said high resistance semiconductor layer is formed of one of materials selected among a group of an undoped semiconductor, a semiconductor having accepter concentration of less than or equal to 5×10 17 cm -3 and a semiconductor doped with Fe, Cr, Ti or Co.
Claim 5
Dependent Claim
24 words
A semiconductor photonic integrated circuit as set forth in claim 1, wherein said first and second optical waveguide layer has a quantum well structure.
Claim 6
Dependent Claim
56 words
A semiconductor photonic integrated circuit as set forth in claim 2, wherein said high resistance semiconductor layer is formed of one of materials selected among a group of an undoped semiconductor, a semiconductor having accepter concentration of less than or equal to 5×10 17 cm -3 and a semiconductor doped with Fe, Cr, Ti or Co.
Claim 7
Dependent Claim
24 words
A semiconductor photonic integrated circuit as set forth in claim 2, wherein said first and second optical waveguide layer has a quantum well structure.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-29 | 2001-06-30 | 2001-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-29 | 2005-06-30 | 2005-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-29 | 2009-06-30 | 2009-12-30 | $7700.00 | Window Closed / Lapsed |