Method and apparatus for upscaling video images when pixel data used for upscaling a source video image are unavailable

Claim 2

A graphics controller circuit for upscaling a source video image to generate an upscaled video image, wherein the source video image comprises at least a one scan line and an another scan line represented by a set of source video pixel data, said graphics controller circuit comprising: an interpolator generating a set of additional pixel data comprised in the upscaled video image by interpolating the source video pixel data of the one scan line and the another scan line; a first circuit for determining a condition in which at least one of the source video pixel data of the another scan line are unavailable for interpolation by said interpolator; and a control circuit to cause said interpolator to generate the set of additional pixel data from the source video pixel data of only the one scan line when the source video pixel data of the another scan line are unavailable.

Claim 3

The graphics controller circuit of claim 1 further comprising a bus coupling a memory to said interpolator, wherein said memory stores the source video pixel data of the another scan line and provides the source video pixel data of the another scan line to said interpolator over the bus, and wherein the condition comprises bandwidth unavailability on said bus to transfer the source video pixel data to said interpolator from said memory.

Claim 4

The graphics controller circuit of claim 2 further comprising a FIFO module including a plurality of FIFOs for buffering data transferred to and from said memory, and wherein said first circuit determines said condition by examining data levels in the plurality of FIFOs.

Claim 5

The graphics controller circuit of claim 3 wherein said FIFO module sends to said control circuit a first signal upon detecting a first type of data level in the plurality of FIFOs, and a second signal upon detecting a second type of data level in the plurality of FIFOs.

Claim 6

The graphics controller circuit of claim 4 wherein said control circuit causes said interpolator to generate the additional pixel data from only a subset of the source video pixel data in the one scan line in response to the second signal, and from all of the source video pixel data in the one scan line in response to the first signal.

Claim 7

The graphics controller circuit of claim 5 wherein the subset of the source video pixel data in the one scan line comprises alternate source video pixel data in the one scan line.

Claim 8

A computer system for displaying a source video image comprising a one scan line and an another scan line represented by a set of source video pixel data, the computer system comprising: a display unit for displaying an upscaled video image corresponding to the source video image; a display memory for storing the set of source video pixel data; and a graphics controller circuit for generating display signals to said display unit, said graphics controller circuit further comprising: a host interface for receiving the set of source video pixel data from said display memory; an interpolator generating a set of additional pixel data comprised in the upscaled video image by interpolating the source video pixel data of the one scan line and the another scan line; a first circuit for determining a condition in which at least one of the source video pixel data of the another scan line are unavailable for interpolation by said interpolator; and a control circuit to cause said interpolator to generate the set of additional pixel data from the source video pixel data of only the one scan line when the source video pixel data of the another scan line are unavailable.

Claim 9

A computer system for displaying a source video image comprising a one scan line and an another scan line represented by a set of source video pixel data, the computer system comprising: a display unit for displaying an upscaled video image corresponding to the source video image; a display memory for storing the set of source video pixel data; and a graphics controller circuit for generating display signals to said display unit, said graphics controller circuit further comprising: a host interface for receiving the set of source video pixel data from said display memory; an interpolator generating a set of additional pixel data comprised in the upscaled video image by interpolating the source video pixel data of the one scan line and the another scan line; a first circuit for determining a condition in which at least one of the source video pixel data of the another scan line are unavailable for interpolation by said interpolator; and a control circuit to cause said interpolator to generate the set of additional pixel data from the source video pixel data of only the one scan line when the source video pixel data of the another scan line are unavailable.

Claim 10

The computer system of claim 7 further comprising a bus coupling said memory to said host interface, wherein the condition comprises bandwidth unavailability on said bus to transfer the source video pixel data to said interpolator from said memory.

Claim 11

The computer system of claim 8 further comprising a FIFO module including a plurality of FIFOs for buffering data transferred to and from said memory, and wherein said first circuit determines said condition by examining data levels in the plurality of FIFOs.

Claim 12

The computer system of claim 9 wherein said FIFO module sends to said control circuit a first signal upon detecting a first type of data level in the plurality of FIFOs, and a second signal upon detecting a second type of data level in the plurality of FIFOs.

Claim 13

The computer system of claim 10 wherein said control circuit causes said interpolator to generate the additional pixel data from only a subset of the source video pixel data in the one scan line in response to the second signal, and from all of the source video pixel data in the one scan line in response to the first signal.

Claim 14

The computer system of claim 11 wherein the subset of the source video pixel data in the one scan line comprises alternate source video pixel data in the one scan line.

Claim 17

The method of claim 13 further comprising the steps of: storing the source video pixel data of the another scan line in a memory; providing the source video pixel data stored in the memory to said step of generating a set of additional pixel data over a bus; wherein said step of determining comprises determining whether the bus had sufficient bandwidth to transfer bus to transfer the source video pixel data stored in the memory to said step of generating a set of additional pixel data.

Claim 18

The method of claim 14 wherein said step of determining comprises examining data levels in a plurality of FIFOs comprised in a FIFO module.

Claim 19

The method of claim 15 further comprising the step of generating a first signal upon detecting a first type of data level in the plurality of FIFOs, and a second signal upon detecting a second type of data level in the plurality of FIFOs.

Claim 20

The method of claim 16 said step of generating the set of additional pixel data further comprises the steps of: generating the additional pixel data from only a subset of the source video pixel data in the one scan line in response to the second signal; and generating the additional pixel data from all the source video pixel data in the one scan line in response to the first signal.

Claim 21

The method of claim 17 wherein the subset of the source video pixel data in the one scan line comprises alternate source video pixel data in the one scan line.